AD7660 Analog Devices, AD7660 Datasheet
AD7660
Specifications of AD7660
Available stocks
Related parts for AD7660
AD7660 Summary of contents
Page 1
... The AD7660 has a maximum integral nonlinearity of 3 LSBs with no missing 16-bit code. 3. Single-Supply Operation The AD7660 operates from a single 5 V supply and only dissipates 21 mW typical. Its power dissipation decreases with the throughput to, for instance, only 100 SPS throughput. It consumes 7 mW maximum when in power-down. ...
Page 2
... AD7660–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes 2 Transition Noise 3 Full-Scale Error 3 Unipolar Zero Error Power Supply Sensitivity ...
Page 3
... AD7660 Typ Max +85 Min Typ Max 500 9.5 4 3.2 1.5 50 ...
Page 4
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7660 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 5
... SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7660 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK ...
Page 6
... DI enabled also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7660. Current conversion, if any, is aborted Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver- sions are inhibited after the current one is completed. ...
Page 7
... CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7660 to achieve its rated accuracy after a full-scale step function is applied to its input. Overvoltage Recovery The time required for the ADC to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value ...
Page 8
... Performance Characteristics AD7660 –1 –2 –3 0 16384 32768 49152 65536 CODE TPC 1. Integral Nonlinearity vs. Code 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 0 16384 32768 49152 65536 CODE TPC 4. Differential Nonlinearity vs. Code 0 4096 POINT FFT – 100kHz 45kHz –40 IN SNR = 90.14dB SINAD = 89.94dB – ...
Page 9
... AVDD 10 0 OVDD –10 –40 – 110 TEMPERATURE – C TPC 14. Power-Down Operating Currents vs. Temperature –9– AD7660 50 40 OVDD @ 2.7V OVDD @ 2.7V OVDD @ 5V OVDD @ 5V 100 150 200 C – TPC 12. Typical Delay vs. Load ...
Page 10
... ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7660 can be operated from a single 5 V supply and be interfaced to either digital logic housed in a 48-lead LQFP package or a 48-lead LFCSP package that com- bines space savings and allows flexible configurations as either serial or parallel interface ...
Page 11
... Using the OB/2C digital input, the AD7660 offers two output codings: straight binary and twos complement. The LSB size is /65536, which is about 38.15 mV. The ideal transfer charac- V REF teristic for the AD7660 is shown in Figure 4 and Table II. 1 LSB = V /65536 REF 111...111 111...110 111 ...
Page 12
... During the conversion phase, where the switches are opened, the input impedance is limited to C1. It has to be noted that the input impedance of the AD7660, unlike other SAR ADCs, is not a pure capacitance and thus, inherently reduces the kickback transient at the beginning of the acquisition phase. The R1, C2 makes a one- pole low-pass filter with a typical cutoff frequency of 820 kHz that reduces undesirable aliasing effect and limits the noise ...
Page 13
... The AD780 can be selected with reference voltage. Power Supply The AD7660 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and 5.25 V. ...
Page 14
... The serial interface is multiplexed on the parallel data bus. The AD7660 digital interface also accommodates both logic by simply connecting the OVDD supply pin of the AD7660 to the host system interface digital supply. Finally, by using the OB/2C input pin, both twos complement or straight binary coding can be used ...
Page 15
... Internal Clock The AD7660 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held LOW. The AD7660 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired ...
Page 16
... SCLK of the one used to shift out the data on SDOUT. Therefore, the MSB of the “upstream” converter just follows the LSB of the “downstream” converter on the next SCLK cycle AD7660s running at 100 kSPS can be daisy-chained using this method. AD7660 ...
Page 17
... Figure 21 shows an interface diagram between the AD7660 and an SPI-equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7660 acts as a slave device and data must be read after conversion. This mode also allows the daisy- chain feature. The convert command can be initiated in response to an internal timer interrupt ...
Page 18
... Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supply lines to the AD7660 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’ ...
Page 19
... Frame Chip Scale Package [LFCSP] (CP-48) Dimensions shown in millimeters 0.60 MAX 0.60 MAX 37 36 6.75 BOTTOM BSC SQ 0.50 0. 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC COPLANARITY 0.20 REF 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 –19– AD7660 9.00 BSC PIN 1 TOP VIEW 7.00 BSC SQ (PINS DOWN 0.27 0.22 0.17 0.30 0.23 0.18 PIN 1 INDICATOR 48 1 5.25 5.10 SQ VIEW 4 ...
Page 20
... AD7660 Revision History Location 10/03—Data Sheet changed from REV REV. D. Update format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Changes to Table Added PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Added Overvoltage Recovery section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Added TPC Changes to CIRCUIT INFORMATION section ...