AD73360

Manufacturer Part NumberAD73360
Description6-Channel AFE Processor for General Purpose Applications Including Industrial Power Metering or Multi-Channel Analog Inputs
ManufacturerAnalog Devices
AD73360 datasheet
 


Specifications of AD73360

Resolution (bits)16bit# Chan6
Sample Rate2.05MSPSInterfaceSer
Analog Input TypeDiff-Uni,SE-UniAin Range1.6 V p-p,3.2 V p-p
Adc ArchitectureSigma-DeltaPkg TypeQFP,SOIC
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FEATURES
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
77 dB SNR
64 kS/s Maximum Sample Rate
–83 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel)
Programmable Input Gain
Flexible Serial Port which Allows Multiple Devices to
Be Connected in Cascade
Single (+2.7 V to +5.5 V) Supply Operation
80 mW Max Power Consumption at +2.7 V
On-Chip Reference
28-Lead SOIC and 44-Lead TQFP Packages
APPLICATIONS
General Purpose Analog Input
Industrial Power Metering
Motor Control
Simultaneous Sampling Applications
GENERAL DESCRIPTION
The AD73360 is a six-input channel analog front-end processor
for general purpose applications including industrial power
VINP1
SIGNAL
CONDITIONING
VINN1
VINP2
SIGNAL
CONDITIONING
VINN2
VINP3
SIGNAL
CONDITIONING
VINN3
REFCAP
REFOUT
VINP4
SIGNAL
CONDITIONING
VINN4
VINP5
SIGNAL
CONDITIONING
VINN5
VINP6
SIGNAL
CONDITIONING
VINN6
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
metering or multichannel analog inputs. It features six 16-bit
A/D conversion channels each of which provide 77 dB signal-to-
noise ratio over a dc to 4 kHz signal bandwidth. Each channel
also features a programmable input gain amplifier (PGA) with
gain settings in eight stages from 0 dB to 38 dB.
The AD73360 is particularly suitable for industrial power me-
tering as each channel samples synchronously, ensuring that there
is no (phase) delay between the conversions. The AD73360 also
features low group delay conversions on all channels.
An on-chip reference voltage is included and is programmable
to accommodate either 3 V or 5 V operation.
The sampling rate of the device is programmable with four
separate settings offering 64 kHz, 32 kHz, 16 kHz and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73360 is available in 28-lead SOIC and 44-lead TQFP
packages.
FUNCTIONAL BLOCK DIAGRAM
ANALOG
0/38dB
DECIMATOR
-
PGA
MODULATOR
ANALOG
0/38dB
-
DECIMATOR
PGA
MODULATOR
ANALOG
0/38dB
DECIMATOR
-
PGA
MODULATOR
REFERENCE
AD73360
ANALOG
0/38dB
DECIMATOR
-
PGA
MODULATOR
ANALOG
0/38dB
-
DECIMATOR
PGA
MODULATOR
ANALOG
0/38dB
DECIMATOR
-
PGA
MODULATOR
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
Six-Input Channel
Analog Front End
AD73360
SDI
SDIFS
SCLK
RESET
SERIAL
I/O
MCLK
PORT
SE
SDO
SDOFS
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000

AD73360 Summary of contents

  • Page 1

    ... A serial port (SPORT) allows easy interfacing of single or cas- caded devices to industry standard DSP engines. The SPORT transfer rate is programmable to allow interfacing to both fast and slow DSP engines. The AD73360 is available in 28-lead SOIC and 44-lead TQFP packages. FUNCTIONAL BLOCK DIAGRAM ANALOG 0/38dB ...

  • Page 2

    ... Typical Output Frequency (Normalized 0.03125 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5 1 (AVDD = 3 V 10%; DVDD = 8.192 MHz kHz; T SCLK S AD73360A Min Typ Max Unit 1.125 1.25 1.375 V 50 ppm/°C Ω 130 1.125 1.25 1.375 V 1 kΩ 100 pF 1.644 V p-p – ...

  • Page 3

    ... NO 1.5 0 YES 0 –3– Test Conditions/Comments |IOUT| ≤ 100 µA |IOUT| ≤ 100 µA See Table I = +85°C. 11 )/DMCLK. Comments REFOUT Disabled REFOUT Disabled MCLK Active Levels Equal and DVDD Digital Inputs Static and Equal DVDD AD73360 ...

  • Page 4

    ... FREQUENCY RESPONSE 7 (ADC) Typical Output Frequency (Normalized 0.03125 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5 1 (AVDD = 5 V 10%; DVDD = 8.192 MHz kHz; T SCLK S AD73360A Min Typ Max Unit 1. ppm/°C Ω 130 1. kΩ 100 pF 3.2875 V p-p 3.17 dBm 2 ...

  • Page 5

    ... V ± 10% 1.25 V 1.25 V ± 10% 1.25 V 1.64375 V p-p 1.64375 V p-p 1.1413 V p-p 1.1413 V p-p –5– AD73360 Test Conditions/Comments |IOUT| ≤ 100 µA |IOUT| ≤ 100 µA See Table II Comments REFOUT Disabled REFOUT Disabled MCLK Active Levels Equal and DVDD Digital Inputs Static and Equal DVDD ...

  • Page 6

    ... AD73360 TIMING CHARACTERISTICS Limit at Parameter T = – + Clock Signals 24 24.4 3 Serial Port 0.4 × 0.4 × TIMING CHARACTERISTICS Limit at Parameter T = – + Clock Signals ...

  • Page 7

    ... Figure 5b. S/(N+D) vs. V Bandwidth (300 Hz–3.4 kHz D15 D14 D15 D2 Figure 4. Serial Port (SPORT) –7– AD73360 –10 –85 –75 –65 –55 –45 –35 –25 –15 V – dBm0 IN (ADC @ 3 V) Over Voiceband ...

  • Page 8

    ... The upgrade consists of a connector for the expansion port P3 of the EZ-KIT Lite. This option is intended for existing owners of EZ-KIT Lite. 4 The EZ-KIT Lite has been modified to allow it to interface with the AD73360 evaluation board. This option is intended for users who do not already have an EZ-KIT Lite. ...

  • Page 9

    ... SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low. SDI Serial Data Input of the AD73360. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low. SE SPORT Enable ...

  • Page 10

    ... BW Bandwidth. CRx A Control Register where placeholder for an alphabetic character (A–E). There are eight read/write control registers on the AD73360— designated CRA through CRE. CRx:n A bit position, where placeholder for a numeric character (0–7), within a control regis- ter; where placeholder for an alphabetic character (A– ...

  • Page 11

    ... Sigma-delta converters employ a technique known as over- sampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73360, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth (Figure 6a) ...

  • Page 12

    ... AD73360 Figure 7 shows the various stages of filtering that are employed in a typical AD73360 application. In Figure 7a we see the trans- fer function of the external analog antialias filter. Even though single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling fre- quency ...

  • Page 13

    ... In both transmit and receive modes, data is transferred at the serial clock (SCLK) rate with the MSB being transferred first. Due to the fact that the SPORT of each AD73360 block uses a common serial register for serial input and output, communica- tions between an AD73360 and a host processor (DSP engine) must always be initiated by the AD73360s themselves ...

  • Page 14

    ... Bits 10–8 Register Address This 3-bit field is used to select one of the eight control registers on the AD73360. Bits 7–0 Register Data This 8-bit field holds the data that written to or read from the selected register provided the address field is zero ...

  • Page 15

    ... Reserved Must Be Programmed to Zero (0) Reserved Must Be Programmed to Zero (0) PUREF REF Power (0 = Power Down Power Up) RU REFOUT Use (0 = Disable REFOUT Enable REFOUT) 5VEN Enable 5 V Operating Mode (0 = Disable 5 V Mode Enable 5 V Mode) –15– AD73360 – MM DATA/PGM SCD1 ...

  • Page 16

    ... AD73360 CONTROL REGISTER D PUI2 Bit Name CONTROL REGISTER E PUI4 Bit Name CONTROL REGISTER F PUI6 Bit Name Table X. Control Register D Description I2GS2 I2GS1 I2GS0 Description I1GS0 ADC1:Input Gain Select (Bit 0) ...

  • Page 17

    ... Master Clock Divider. These bits are used to set the Master Clock Divider ratio. See Table V. CRB:7 Control Echo Enable. Setting this bit will cause the AD73360 to write out any control words it receives. This is used as a diagnostic mode. This bit should be set to 0 for correct operation in Mixed Mode or Data Mode. ...

  • Page 18

    ... Control Register C CRC:0 Global Power-Up. Writing this bit will cause all six channels of the AD73360 to power-up regardless of the status of the Power Control Bits in CRD-CRF. If less than six channels are required, this bit should be set to 0 and the Power Control Bits of the relevant channels should be set to 1. ...

  • Page 19

    ... The AD73360 inputs and outputs data in a Time Division Multiplexing (TDM) format. When data is being read from the AD73360 each channel has a fixed time slot in which its data is transmitted channel is not powered up, no data is transmit- ted during the allocated time slot and the SDO line will be three-stated ...

  • Page 20

    ... DSP engine. This 3-bit ad- dress format allows the user to uniquely address any one eight devices in a cascade. If the AD73360 is used in a stand- alone configuration connected to a DSP, the device address corresponds to 0. If, on the other hand, the AD73360 is config- ured in a cascade of multiple devices, its device address corre- sponds with its hardwired position in the cascade ...

  • Page 21

    ... Data Mode. Note that when programming the DSP in this configuration it is advisable to preload the Tx register with the first control word to be sent before the AD73360 is taken out of reset. This ensures that this word will be transmitted to coincide with the first output word from the device(s). ...

  • Page 22

    ... AD73360 SE SCLK SDOFS UNDEFINED DATA SDO SDIFS CONTROL WORD SDI Figure 15a. Interface Signal Timing for Program Mode Operation (Writing to a Register) SE SCLK SDOFS SDO UNDEFINED DATA SDIFS SDI REGISTER READ INSTRUCTION Figure 15b. Interface Signal Timing for Program Mode Operation (Reading a Register) ...

  • Page 23

    ... Cascade Operation The AD73360 has been designed to support up to eight devices in a cascade connected to a single serial port (see Figure 17). The SPORT interface protocol has been designed so that device addressing is built into the packet of information sent to the device. This allows the cascade to be formed with no extra hard- ware overhead for control signals or addressing ...

  • Page 24

    ... Figure 19. SE and RESET Sync Circuit for Cascaded Operation PERFORMANCE As the AD73360 is designed to provide high performance, low cost conversion important to understand the means by which this high performance can be achieved in a typical appli- cation. This section will, by means of spectral graphs, outline ...

  • Page 25

    ... AD73360 to be used with either a single-ended or differential signal. The applied signal can also be inverted internally by the AD73360 if required. The analog input signal to the AD73360 can be dc-coupled, pro- vided that the dc bias level of the input signal is the same as the internal reference level (REFOUT) ...

  • Page 26

    ... The analog ground plane should be allowed to run under the AD73360 to avoid noise coupling. The power supply lines to the AD73360 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply lines. Fast switching signals such as ...

  • Page 27

    ... The AD73360, with its six-channel simulta- neous sampling capability, is ideally suited for use in vector motor control applications. A block diagram of a vector motor control application using the AD73360 is shown in Figure 30. The position of the field is derived by determining the current in each phase of the motor ...

  • Page 28

    ... An invalid ADC word is also received at the DSP’s Rx register. Step 3 selects the settings for each channel of the AD73360. This set can be repeated as necessary to pro- gram all the channels to the desired settings. Steps 4 and 5 program the modes of each channel (i.e., single-ended or differ- ential mode and normal or inverted) ...

  • Page 29

    ... No data is read from the AD73360 at this point. Steps 3 and 4 set the reference and places the part into Mixed Mode. In Steps 5 and 6 valid ADC results are read from the AD73360 and in Step 7 the DSP sends an instruction to the AD73360 to change the gain of Channel 1. NOTE 1 This sequence assumes that the DSP SPORT’ ...

  • Page 30

    ... Configuring a Cascade of Two AD73360s to Operate in Data Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73360s to set them up for operation not intended definitive initialization sequence, but will show users the typical input/output events that occur in the programming and operation phases description panel refers to Figure 34 ...

  • Page 31

    ... STEP N+2 DSP Tx REG CONTROL WORD 0111 1111 1111 1111 STEP N+3 *ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS Figure 34. Programming Two AD73360s in Cascade for Data Mode Operation REV. A DEVICE 1 DEVICE 2 ADC WORD 1* ADC WORD 2* 0000 0000 0000 0000 ...

  • Page 32

    ... Configuring a Cascade of Two AD73360s to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73360s to configure them for operation in Mixed Mode not intended defini- tive initialization sequence, but will show users the typical input/ ...

  • Page 33

    ... DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS. **THIS CONTROL WORD IS NOT INTENDED FOR THE DEVICE THAT HAS RECEIVED IT. ITS ADDRESS FIELD WILL BE DECREMENTED AND THE DATA WILL BE TRANSMITTED TO THE NEXT DEVICE IN THE CASCADE. Figure 35. Programming Two AD73360s in Cascade for Mixed Mode REV. A DEVICE 1 ...

  • Page 34

    ... REGISTER BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . 17 Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 19 Decimation Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 19 TABLE OF CONTENTS Page Topic OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Resetting the AD73360 . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program (Control) Mode . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Mixed Program/Data Mode . . . . . . . . . . . . . . . . . . . . . . . 20 INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Digital Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Encoder Section ...

  • Page 35

    ... SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 44-Lead Thin Quad Flatpack (SU-44) 0.047 (1.20) MAX 0.006 (0.15) 0.472 (12.00) SQ 0.002 (0.05 SEATING PLANE TOP VIEW (PINS DOWN 0.041 (1.05) 0.031 (0.80) 0.018 (0.45) BSC 0.037 (0.95) 0.012 (0.30) –35– AD73360 0.0291 (0.74) 45 0.0098 (0.25) 0.0500 (1.27 0.0157 (0.40 0.394 (10. ...