AD73360 Analog Devices, AD73360 Datasheet - Page 25

• Manufacturer Part Number: AD73360
• Description: 6-Channel AFE Processor for General Purpose Applications Including Industrial Power Metering or Multi-Channel Analog Inputs
• Manufacturer: Analog Devices

Specifications of AD73360

• Resolution (bits): 16bit
• # Chan: 6
• Sample Rate: 2.05MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 1.6 V p-p,3.2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP,SOIC

REV. A
Figure 23 shows a comparison of SNR results achieved by vary-
ing either the Decimation Rate Setting or the DMCLK Rate
Settings.
Encoder Group Delay
The AD73360 implementation offers a very low level of group
delay, which is given by the following relationship:
where:
If final filtering is implemented in the DSP, the final filter’s
group delay must be taken into account when calculating overall
group delay.
DESIGN CONSIDERATIONS
Analog Inputs
The AD73360 features six signal conditioning inputs. Each
signal conditioning block allows the AD73360 to be used with
either a single-ended or differential signal. The applied signal
can also be inverted internally by the AD73360 if required. The
analog input signal to the AD73360 can be dc-coupled, pro-
vided that the dc bias level of the input signal is the same as the
internal reference level (REFOUT). Figure 24 shows the recom-
mended differential input circuit for the AD73360. The circuit
of Figure 24 implements first-order low-pass filters with a 3 dB
Figure 23. Comparison of DMCLK and Decimation Rate
Settings
Order is the order of the decimator (= 3),
M is the decimation factor (= 32) and
Tdec is the decimation sample interval (= 1/2.048e6)
=> Group Delay (Decimator) = 3 × (32–1)/2 × (1/2.048e6)
= 22.7 µs
VIN
Group Delay (Decimator) = Order × ((M–1)/2) × Tdec
Figure 24. Example Circuit for Differential Input
(DC Coupling)
TO INPUT BIAS
81
80
79
78
77
76
75
74
73
72
71
CIRCUITRY
8
100
100
0.047 F
16
SAMPLING FREQUENCY – kHz
24
0.1 F
0.047 F
REFOUT
32
DMCLK = MCLK
REFCAP
VINPx
VINNx
40
REDUCED
DMCLK
48
REFERENCE
56
VOLTAGE
64
–25–
point at 34 kHz; these are the only filters that must be imple-
mented external to the AD73360 to prevent aliasing of the
sampled signal. Since the ADC uses a highly oversampled ap-
proach that transfers the bulk of the antialiasing filtering into the
digital domain, the off-chip antialiasing filter need only be of a
low order. It is recommended that for optimum performance the
capacitors used for the antialiasing filter be of high quality di-
electric (NPO).
The AD73360’s on-chip 38 dB preamplifier can be enabled
when there is not enough gain in the input circuit; the preampli-
fier is configured by bits IGS0–2 of CRD. The total gain must
be configured to ensure that a full-scale input signal produces a
signal level at the input to the sigma-delta modulator of the
ADC that does not exceed the maximum input range.
The dc biasing of the analog input signal is accomplished with
an on-chip voltage reference. If the input signal is not biased at
the internal reference level (via REFOUT), then it must be
ac-coupled with external coupling capacitors. CIN should be
0.1 µF or larger. The dc biasing of the input can then be accom-
plished using resistors to REFOUT as in Figure 25.
Figures 26 and 27 detail ac- and dc-coupled input circuits for
single-ended operation respectively.
Figure 26. Example Circuit for Single-Ended Input
(AC Coupling)
Figure 27. Example Circuit for Single-Ended Input
(DC Coupling)
Figure 25. Example Circuit for Differential Input
(AC Coupling)
VIN
VIN
VIN
TO INPUT BIAS
CIRCUITRY
CIN
CIN
CIN
100
0.047 F
0.047 F
0.047 F
100
100
100
0.1 F
0.1 F
10k
0.1 F
10k
REFOUT
REFOUT
0.047 F
REFOUT
10k
REFCAP
VINNx
VINPx
VINPx
VINNx
REFCAP
VINPx
VINNx
REFCAP
AD73360
REFERENCE
REFERENCE
REFERENCE
VOLTAGE
VOLTAGE
VOLTAGE