AD73360 Analog Devices, AD73360 Datasheet - Page 28

• Manufacturer Part Number: AD73360
• Description: 6-Channel AFE Processor for General Purpose Applications Including Industrial Power Metering or Multi-Channel Analog Inputs
• Manufacturer: Analog Devices

Specifications of AD73360

• Resolution (bits): 16bit
• # Chan: 6
• Sample Rate: 2.05MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 1.6 V p-p,3.2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP,SOIC

AD73360
Programming a Single AD73360 for Data Mode Operation
This section describes a typical sequence in programming a
single AD73360 to operate in normal Data Mode. It details the
control (program) words that are sent to the device to configure
its internal registers and shows the typical output data received
during both Program and Data Modes. The device is connected
in Frame Sync Loop-Back Mode (see Figure 13), which forces
an input word from the DSP’s Tx register each time the AD73360
outputs a word via the SDO/SDOFS lines (while the AD73360
is in Program Mode the data transmitted will be invalid ADC
data and will, in fact, be a modified version of the last control
word written in by the DSP). In each case the DSP’s Tx register
is preloaded with the data before the frame pulse is received. In
Step 1, the part has just been reset and on the first output event
the AD73360 presents an invalid output word
register contains a control word that programs CRB with the
data byte 0x03. This sets the sample rate at 8 kHz (with a
*ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS
SET CHANNEL INVERSION
RECEIVE VALID ADC DATA
SET 8kHz SAMPLING
GLOBAL POWER-UP
SET CHANNEL GAINS
SET CHANNEL MODE
SET DATA MODE
STEP 1
STEP 2
STEP 3
STEP 4
STEP 5
STEP 6
STEP 7
1000 0001 0000 0011
1000 0010 0000 0001
1000 0011 1000 1111
1000 0110 0011 1111
1000 0111 0011 1111
1000 0000 0000 0001
0111 1111 1111 1111
Figure 32. Programming a Single AD73360 for Operation in Data Mode
CONTROL WORD
CONTROL WORD
CONTROL WORD
CONTROL WORD
CONTROL WORD
CONTROL WORD
CONTROL WORD
DSP Tx REG
DSP Tx REG
DSP Tx REG
DSP Tx REG
DSP Tx REG
DSP Tx REG
DSP Tx REG
1
. The DSP’s Tx
APPENDIX A
0000 0000 0000 0000
1011 1111 0000 0011
1011 1010 0000 0001
1011 1011 1000 1111
1011 1111 0011 1111
1011 1111 0011 1111
1000 0000 0000 0000
ADC WORD 1*
ADC WORD 1*
ADC WORD 1*
ADC WORD 1*
ADC WORD 1*
ADC WORD 1*
ADC WORD 1
DEVICE 1
DEVICE 1
DEVICE 1
DEVICE 1
DEVICE 1
DEVICE 1
DEVICE 1
–28–
master clock of 16.384 MHz). In Step 2, the control word in
the DSP’s Tx register will cause all the AD73360s channels to
power up. This data is received by the AD73360 with the next
frame sync pulse. An invalid ADC word is also received at the
DSP’s Rx register. Step 3 selects the settings for each channel
of the AD73360. This set can be repeated as necessary to pro-
gram all the channels to the desired settings. Steps 4 and 5
program the modes of each channel (i.e., single-ended or differ-
ential mode and normal or inverted). Step 6 puts the AD73360
into Data Mode and in Step 7 the first valid ADC word is
received.
NOTE
1
This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are
enabled. It is important to ensure there is no latency (separation) between
control words in a cascade configuration. This is especially the case when
programming Control Register B, as it contains settings for SCLK and
DMCLK rates.
0000 0000 0000 0000
1011 1111 0000 0011
1011 1010 0000 0001
1011 1011 1000 1111
1011 1110 0011 1111
1011 1111 0011 1111
1000 0000 0000 0000
ADC WORD 1
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DSP Rx REG
DSP Rx REG
DSP Rx REG
DSP Rx REG
DSP Rx REG
DSP Rx REG
DSP Rx REG
REV. A