AD73360 Analog Devices, AD73360 Datasheet - Page 6

• Manufacturer Part Number: AD73360
• Description: 6-Channel AFE Processor for General Purpose Applications Including Industrial Power Metering or Multi-Channel Analog Inputs
• Manufacturer: Analog Devices

Specifications of AD73360

• Resolution (bits): 16bit
• # Chan: 6
• Sample Rate: 2.05MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 1.6 V p-p,3.2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP,SOIC

AD73360
TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
9
10
11
12
13
Limit at
T
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
Limit at
T
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
1
1
A
A
= –40 C to +85 C
= –40 C to +85 C
1
1
1
1
(AVDD = 5 V
noted)
(AVDD = 3 V
noted)
10%; DVDD = 5 V
10%; DVDD = 3 V
–6–
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
10%; AGND = DGND = 0 V; T
10%; AGND = DGND = 0 V; T
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
A
A
= T
= T
MlN
MlN
to T
to T
MAX
MAX
, unless otherwise
, unless otherwise
REV. A