AD7865 Analog Devices, AD7865 Datasheet
AD7865
Specifications of AD7865
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AD7865 Summary of contents
Page 1
... The AD7865-1 offers the standard industrial ranges of ± and ± the AD7865-2 offers a unipolar range 2 and the AD7865-3 offers the common signal processing input range of ± 2 The part features very tight aperture delay matching between the four input sample and hold amplifiers ...
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... Aperture Delay Matching 2 DYNAMIC PERFORMANCE 3 Signal to (Noise + Distortion) Ratio @ 25°C AD7865-1, AD7865-3 AD7865 MIN MAX AD7865-1, AD7865-3 AD7865 Total Harmonic Distortion 3, 4 Peak Harmonic or Spurious Noise 3 Intermodulation Distortion 2nd Order Terms 3rd Order Terms 3, 5 Channel-to-Channel Isolation DC ACCURACY ...
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... Performance measured through full channel (SHA and ADC). 3 See Terminology. 4 Total Harmonic Distortion and Peak Harmonic or Spurious Noise are specified at –83 dBs for the AD7865-2. 5 Measured between any two channels with the other two channels grounded. 6 Sample tested @ 25°C to ensure compliance. ...
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... AD7865 TIMING CHARACTERISTICS Parameter Versions t 2.4 CONV 3.2 t 0.35 ACQ t No. of Channels BUSY × (t CONV 3 t —External V 1 WAKE-UP REF Read Operation 120 9 180 Write Operation ...
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... DRIVE Analog Input Voltage to AGND AD7865-1 (± Input Range ± AD7865-1 (± Input Range ± AD7865 – +18 V AD7865 – +18 V Reference Input Voltage to AGND . . . –0 Digital Input Voltage to DGND . . . . . –0 Digital Output Voltage to DGND . . . . –0 ...
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... H/S SEL input. When the H/S SEL input is high (choosing software control of the channel selection sequence), this pin assumes its INT/EXT CLK function. When INT/EXT CLK Logic 0, the AD7865 uses its internally generated master clock. When INT/EXT CLK is at Logic 1, the master clock is generated externally to the device and applied to CLK IN. ...
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... DB13–DB6 Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 6. Three-state TTL outputs. Output coding is twos complement for AD7865-1 and AD7865-3, and straight binary for AD7865-2. Positive Supply Voltage for Digital section, 5.0 V ± 5%. A 0.1 µF decoupling capacitor should ...
Page 8
... Negative Gain Error (AD7865-1, AD7865-3) This is the deviation of the first code transition ( 000 001) from the ideal –4 × V ± 10 V), –2 × 1/2 LSB (AD7865 at ± 2.5 V range), after Bipolar Zero –V REF Error has been adjusted out. Track/Hold Acquisition Time ...
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... Thereafter, conversions will be completed on the selected sub- set of the four channels. The part accepts an analog input range of ± ± (AD7865-1 2 (AD7865-2) and ± 2.5 V (AD7865-3). Overvoltage protection on the analog inputs for the part allows the input voltage ± ...
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... LSB +FSR/2 – 7/2 LSB AGND + 5/2 LSB AGND + 3/2 LSB AGND – 1/2 LSB NOTES 1 FSR is full-scale range and 2.5 V and for AD7865-2 with V = 2.5 V. REF 2 1 LSB = FSR/16384 and is 0.153 2.5 V) and 0.305 for AD7865-2) with ...
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... V INxA TRACK/ V HOLD INxB For the AD7865- kΩ and kΩ result, the V input should be driven from a low impedance source. The INxA resistor input stage is followed by the high input impedance stage of the track/hold amplifier. The designed code transitions take place midway between suc- cessive integer LSB values (i ...
Page 12
... Figure 7 shows the timing and control sequence required to obtain the optimum throughput rate from the AD7865. To obtain the optimum throughput from the AD7865 the user must read the result of each conversion as it becomes available. The timing diagram in Figure 7 shows a read operation each time the EOC signal goes logic low ...
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... Notice also that a “Quiet Time” is needed before the start of the next conversion sequence. t BUSY IN1 IN2 IN3 t 10 AD7865 . Thus the output data registers acts as a IN1 QUIET TIME IN4 IN1 t 10 IN1 ...
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... AD7865 spends in standby mode. For standby times of less than 10 ms the AD7865 will wake up in less than 5 µs (see Fig- ure 11). For standby times greater than this some or all of the charge on the external reference capacitor will have leaked away and the wake-up time will be dependent on how long it takes to recharge ...
Page 15
... For example, with a throughput rate of 10 kSPS and external reference, the AD7865 will be powered up 11 µs out of every 100 µs (1 µs for wake-up time and 9.6 µs to convert four channels. Therefore, the average power consumption drops to (115 mW × 10.6 ...
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... Fast Fourier Transform (FFT) plot is generated from which the SNR data can be obtained. Figure 15 shows a typical 4096- point FFT plot of the AD7865 with an input signal of 100 kHz and a sampling frequency of 350 kHz. The SNR obtained from this graph is 80.5 dB. It should be noted that the harmonics are taken into account when calculating the SNR ...
Page 17
... The CS signal to the AD7865 derived from the DS signal and a decode of the address bus. This maps the AD7865 into external data memory. The RD signal from the TMS320 is used to enable the ADC data onto the data bus. The AD7865 12000 16383 has a fast parallel bus so there are no wait state requirements. ...
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... R/W D0–D13 ADDITIONAL PINS OMITTED FOR CLARITY MULTIPLE AD7865s IN A SYSTEM Figure 23 shows a system where a number of AD7865s can be configured to handle multiple input channels. This type of con- figuration is common in applications such as sonar, radar, etc. The AD7865 is specified with maximum limits on aperture delay match. This means that the user knows the difference in the sampling instant between all channels ...
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... OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Quad Flatpack (S-44) 0.548 (13.925) 0.546 (13.875) 0.096 (2.44) 0.398 (10.11) MAX 0.390 (9.91) 0.037 (0.94) 8 0.025 (0.64) 33 0.8 34 SEATING PLANE TOP VIEW (PINS DOWN 0.040 (1.02) 0.040 (1.02) 0.032 (0.81) 0.032 (0.81) 0.033 (0.84) 0.083 (2.11) 0.029 (0.74) 0.077 (1.96) AD7865 0.016 (0.41) 0.012 (0.30) ...