AD6640 Analog Devices, AD6640 Datasheet - Page 11

• Manufacturer Part Number: AD6640
• Description: Multi-Channel, Multi-Mode Receiver Chipset
• Manufacturer: Analog Devices

Specifications of AD6640

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 65MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

REV. A
THEORY OF OPERATION
The AD6640 analog-to-digital converter (ADC) employs a two-
stage subrange architecture. This design approach ensures
12-bit accuracy, without the need for laser trim, at low power.
As shown in the functional block diagram, the AD6640 has
complementary analog input pins, AIN and AIN. Each analog
input is centered at 2.4 V and should swing ± 0.5 V around this
reference (see Figure 2). Since AIN and AIN are 180 degrees out
of phase, the differential analog input signal is 2 V p-p.
Both analog inputs are buffered prior to the first track-and-hold,
TH1. The high state of the ENCODE pulse places TH1 in hold
mode. The held value of TH1 is applied to the input of a 6-bit
coarse ADC. The digital output of the coarse ADC drives a
6-bit DAC; the DAC is 12 bits accurate. The output of the 6-bit
DAC is subtracted from the delayed analog signal at the input
of TH3 to generate a residue signal. TH2 is used as an analog
pipeline to null out the digital delay of the coarse ADC.
The 6-bit coarse ADC word and 7-bit residue word are added
together and corrected in the digital error correction logic to
generate the output word. The result is a 12-bit parallel digital
CMOS compatible word, coded as twos complement.
APPLYING THE AD6640
Encoding the AD6640
A valid ENCODE clock must be present on the AD6640 before
the application of AV
driving the ENCODE pins differentially. However, the AD6640
is also designed to interface with TTL and CMOS logic families.
The source used to drive the ENCODE pin(s) must be clean
and free from jitter. Sources with excessive jitter will limit SNR
(see the first equation under the Noise Floor and SNR section).
The AD6640 ENCODE inputs are connected to a differential
input stage (see Figure 3). With no input signal connected to
either ENCODE pin, the voltage dividers bias the inputs to
1.6 V. For TTL or CMOS usage, the ENCODE source should
be connected to ENCODE, Pin 3. ENCODE should be decoupled
using a low inductance or microwave chip capacitor to ground.
If a logic threshold other than the nominal 1.6 V is required,
the following equations show how to use an external resistor,
Rx, to raise or lower the trip point (see Figure 3; R1 = 17 kΩ
and R2 = 8 kΩ).
V
l
=
R1R2 + R1Rx + R2Rx
Figure 7. Single-Ended TTL /CMOS ENCODE
5R2Rx
TTL OR CMOS
SOURCE
CC
0.01 F
(5 V). Best performance is obtained by
to lower logic threshold.
ENCODE
ENCODE
AD6640
–11–
A clean sine wave may be substituted for a TTL clock. In this
case, the matching network is shown. Select a transformer ratio
to match source and load impedances. The input impedance of
the AD6640 ENCODE is approximately 11 kΩ differentially.
Therefore the “R,” shown in the Figure 11, may be any value
that is convenient for available drive power.
While the single-ended ENCODE will work well for many appli-
cations, driving the ENCODE differentially will provide increased
performance. Depending on circuit layout and system noise, a 1 dB
to 3 dB improvement in SNR can be realized. It is not recom-
mended that differential TTL logic be used because most TTL
families that support complementary outputs are not delay or
slew rate matched. Instead, it is recommended that the ENCODE
signal be ac-coupled into the ENCODE and ENCODE pins.
The simplest option is shown below. The low jitter TTL signal is
coupled with a limiting resistor, typically 100 Ω, to the primary
side of an RF transformer (these transformers are inexpensive
and readily available; part number in Figure 10 is from Mini-
Circuits). The secondary side is connected to the ENCODE
and ENCODE pins of the converter. Since both ENCODE
inputs are self-biased, no additional components are required.
Figure 8. Lower Logic Threshold for ENCODE
Figure 9. Raise Logic Threshold for ENCODE
Figure 10. TTL Source–Differential ENCODE
V
l
TTL
=
0.01 F
ENCODE
SOURCE
ENCODE
SOURCE
R
100
2
+
5 2
0.01 F
R
R
0.1 F
R Rx
1
1
Rx
+
Rx
V
AV
l
Rx
V
T1–1T
CC
l
to raise logic threshold.
ENCODE
ENCODE
ENCODE
ENCODE
AD6640
AD6640
ENCODE
ENCODE
5V
5V
AD6640
R2
R1
R1
R2
AD6640