AD6640 Analog Devices, AD6640 Datasheet - Page 14

• Manufacturer Part Number: AD6640
• Description: Multi-Channel, Multi-Mode Receiver Chipset
• Manufacturer: Analog Devices

Specifications of AD6640

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 65MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

AD6640
AD6640 output data is latched using 74LCX574 (U3, U4)
latches following 348 Ω series resistors. The resistors limit the
current that would otherwise flow due to the digital output slew
rate. The resistor value was chosen to represent a time constant
of ~25% of the data rate at 65 MHz. This reduces slew rate
while not appreciably distorting the data waveform. Data is
latched in a pipeline configuration; a rising edge generates the
new AD6640 data sample, latches the previous data at the con-
verter output, and strobes the external data register over J3.
Note that power and ground must be applied to J3 to power the
digital logic section of the evaluation board.
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Quantity
2
11
2
1
3
1
25
1
1
2
1
1
2
1
1
2
2
Reference
+5 VA, GND
C7–C9, C11–C17, C19
C4, C6
J3
J1, J2, J4
R1
R2–R14, R20–R25, R30–R35
R15
R16
T1, T2
U1
DUT
U3, U4
U5
C1, C18
C2, C3
CR1, CR2
Table I. AD6640ST/PCB Bill of Material
–14–
Description
Banana Jack
Ceramic Chip Capacitor 0805, 0.1 µF
Tantalum Chip Capacitor 10 µF
40-Lead Double Row Male Header
BNC Coaxial PCB Connector
Surface Mount Resistor 1206, 348 Ω
Surface Mount Resistor 1206, 348 Ω
Surface Mount Resistor 1206, 100 Ω
Surface Mount Resistor 1206, 270 Ω
Surface Mount Transformer Mini-Circuits T4–1T, 1:4 Ratio
Clock Oscillator (Optional)
AD6640AST 12-Bit–65 MSPS A/D Converter
74LCX574 Octal Latch
74LVQ00 Quad Two Input NAND Gate
Ceramic Chip Capacitor 0508, 0.01 µF Low Inductance
Ceramic Chip Capacitor 0508, 0.1 µF Low Inductance
1N2810 Schottky Diode
DIGITAL WIDEBAND RECEIVERS
Introduction
Several key technologies are now being introduced that may
forever alter the vision of radio. Figure 25 shows the typical dual
conversion superheterodyne receiver. The signal picked up by
the antenna is mixed down to an intermediate frequency (IF)
using a mixer with a variable local oscillator (LO); the variable
LO is used to “tune-in” the desired signal. This first IF is
mixed down to a second IF using another mixer stage and a
fixed LO. Demodulation takes place at the second or third IF
using either analog or digital techniques.
REV. A