AD7730L Analog Devices, AD7730L Datasheet
AD7730L
Specifications of AD7730L
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AD7730L Summary of contents
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... C and a gain drift of less than 2 ppm/ C. The AD7730 is available in a 24-pin plastic DIP, a 24-lead SOIC and 24-lead TSSOP package. The AD7730L is available in a 24-lead SOIC and 24-lead TSSOP package. NOTE The description of the functions and operation given in this data sheet apply to both the AD7730 and AD7730L ...
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AD7730–SPECIFICATIONS Parameter STATIC PERFORMANCE (CHP = Missing Codes 2 Output Noise and Update Rates Integral Nonlinearity 2 Offset Error 2 Offset Drift vs. Temperature 4 Offset Drift vs. Time 2, 5 Positive Full-Scale Error ...
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... Typically 10 A. External MCLK max All Input Ranges Except +10 mV and 10 mV 125 mW max Input Ranges +10 mV and 10 mV Only 125 W max Typically 50 W. External MCLK –3– AD7730/AD7730L = + ...
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... AD7730/AD7730L NOTES 11 Temperature range: – + Sample tested during initial release. 13 The offset (or zero) numbers with CHP = 1 are typically 3 V precalibration. Internal zero-scale calibration reduces this by about 1 V. Offset numbers with CHP = 0 can precalibration. Internal zero-scale calibration reduces this typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the noise ...
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... Evaluation Board – +85 C Small Outline – +85 C Thin Shrink Small Outline Evaluation Board I (800 SINK 100 OUTPUT PIN 50pF I (200 SOURCE 100 –5– AD7730/AD7730L Package Options N-24 R-24 RU-24 R-24 RU- +3V) DD +1. +3V) DD WARNING! ESD SENSITIVE DEVICE ...
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... AD7730/AD7730L BUFFER AMPLIFIER THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS ALLOWING SIGNIFICANT EXTERNAL SOURCE IMPEDANCES SEE PAGE 24 BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TO EASILY DETECT TRANSDUCER HAS BURNT OUT OR GONE OPEN-CIRCUIT ...
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... MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The AD7730 is specified with a clock input frequency of 4.9152 MHz while the AD7730L is specified with a clock input frequency of 2.4576 MHz. ...
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... AD7730/AD7730L Pin No. Mnemonic Function 3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock sig- nal. This clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving one CMOS load ...
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... The two points used to calculate the gain error are full scale and zero scale. REV. A AD7730/AD7730L BIPOLAR NEGATIVE FULL-SCALE ERROR This is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) – V /GAIN + 0 ...
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... AD7730/AD7730L OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7730 can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or dc-excited applications optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. These options are discussed in more detail in later sections. The chop mode has the advantage of lower drift numbers and better noise im- munity, but the noise is approximately 20% higher for a given – ...
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... DATA REGISTER DIN MODE REGISTER DIN FILTER REGISTER DIN DAC REGISTER DIN OFFSET REGISTER (x3) DIN GAIN REGISTER (x3) DIN TEST REGISTER Figure 4. Register Overview –11– AD7730/AD7730L Input Range Input Range Input Range = 110 80 60 130 95 75 145 100 ...
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... AD7730/AD7730L Register Name Type Size Communications Write Only 8 Bits Register WEN ZERO RW1 RW0 ZERO Status Register Read Only 8 Bits RDY STDY STBY NOREF MS3 Data Register Read Only 16 Bits or 24 Bits Mode Register Read/Write 16 Bits B/U MD2 MD1 MD0 DEN HIREF ...
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... CR2 RW1 RW0 ZERO RS2 Table VII. Read/Write Mode RW1 RW0 Read/Write Mode 0 0 Single Write to Specified Register 0 1 Single Read of Specified Register 1 0 Start Continuous Read of Specified Register 1 1 Stop Continuous Read Mode –13– AD7730/AD7730L CR1 CR0 RS1 RS0 ...
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... AD7730/AD7730L Bit Bit Location Mnemonic Description CR3 ZERO A zero must be written to this bit to ensure correct operation of the AD7730. CR2–CR0 RS2–RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select which register type the next read or write operation operates upon as shown in Table VIII. ...
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... Single Conversion Mode 1 1 Power-Down (Standby) Mode 0 0 Internal Zero-Scale Calibration 0 1 Internal Full-Scale Calibration 1 0 System Zero-Scale Calibration 1 1 System Full-Scale Calibration –15– AD7730/AD7730L MR10 MR9 MR8 D1 (0) D0 (0) WL (1) MR2 MR1 MR0 BO (0) CH1 (0) CH0 (0) Power-On/Reset Default ...
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... AD7730/AD7730L MD2 MD1 MD0 Operating Mode Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7730 is not processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC input pin. However, exerting the SYNC pin does not actually force these mode bits The part returns to this mode after a calibration or after a conversion in Single Conversion Mode ...
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... CLKDIS bit is active. REV. A Table XII. Input Range Selection Input Range B/U Bit = 0 RN0 0 – + – + – + – +80 mV –17– AD7730/AD7730L B/U Bit = + + + +80 mV Power-On/Reset Default ...
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... Filter Architecture section). The allowable range for SF words depends on whether the part is operated with CHOP on or off and SKIP on or off. Table XV outlines the SF ranges for different setups. All output update rates will be one-half those quoted in Table XV for the AD7730L operating with a 2.4576 MHz clock. ...
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... AD7730 output. The number of sinc SF) where DL is the value loaded to bits DL0–DL3. 3 filter must settle every chop cycle. With CHP = 0, –19– AD7730/AD7730L filter followed by a 22-tap FIR filter. With fed directly 3 filter. Initially, 3 ...
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... AD7730/AD7730L DAC Register (RS2–RS0 = 1, 0, 0); Power On/Reset Status: 20 Hex The DAC Register is an 8-bit register from which data can either be read or to which data can be written. This register provides the code for the offset-compensation DAC on the part. Table XVI outlines the bit designations for the DAC Register. DR0 through DR7 indicate the bit location, DR denoting the bits are in the DAC Register ...
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... READ REGISTER STOP CONTINUOUS READ OPERATION? YES WRITE BYTE Z TO Register Communications Register Data Register Mode Register Filter Register DAC Register Offset Register Gain Register Test Register –21– AD7730/AD7730L Byte W Byte Y Byte Z (Hex) (Hex) (Hex ...
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... AD7730/AD7730L CALIBRATION OPERATION SUMMARY The AD7730 contains a number of calibration options as outlined previously. Table XVII summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method software poll of the RDY bit in the Status Register ...
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... Yes Yes 011 Yes Yes As Is Yes No 000 Yes No New Initial No Value Reset 000 Yes –23– AD7730/AD7730L . DD Reset Serial Set RDY Set STDY Interface Pin/Bit Bit Yes Yes Yes Yes Yes Yes No Yes Yes No Yes Yes No Yes Yes ...
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... AD7730/AD7730L ANALOG INPUT Analog Input Channels The AD7730 contains two differential analog input channels, a primary input channel, AIN1, and a secondary input channel, AIN2. The input pairs provide programmable gain, differential channels which can handle either unipolar or bipolar input signals. It should be noted that the bipolar input signals are referenced to the respective AIN(– ...
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... REF bit becomes active, the part places all ones in the Data Register. Therefore not necessary to continuously monitor the status of the NO REF bit when performing conversions only necessary to verify its status if the conversion result read from the Data Register is all 1s. –25– AD7730/AD7730L REF IN(+) REF IN(– ...
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... AD7730/AD7730L If the AD7730 is performing either an offset or gain calibration and the NOREF bit becomes active, the updating of the respec- tive calibration register is inhibited to avoid loading incorrect coefficients to this register. If the user is concerned about verify- ing that a valid reference is in place every time a calibration is performed, then the status of the NOREF bit should be checked at the end of the calibration cycle ...
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... SF Figure 12. Expanded Full Frequency Response of AD7730 (Second Stage Filter as Normal FIR, Chop Enabled –27– AD7730/AD7730L FREQUENCY – 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY – ...
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... AD7730/AD7730L Because of this effect, care should be taken in choosing an out- put rate that is close to the line frequency in the application. If the line frequency is 50 Hz, an output update rate should not be chosen as it will significantly reduce the AD7730’s line frequency rejection (the 50 Hz will appear effect with only 6 dB attenuation). Choosing an output rate will result dB— ...
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... E PROM. The values in these calibration registers are 24 bits wide. In addition, the span and offset for the part can be adjusted by the user. –29– AD7730/AD7730L mode, the part has settled to the new value much FASTStep mode settles to FASTStep FASTStep mode and ...
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... AD7730/AD7730L Internally in the AD7730, the coefficients are normalized before being used to scale the words coming out of the digital filter. The offset calibration register contains a value which, when normalized, is subtracted from all conversion results. The gain calibration register contains a value which, when normalized, is multiplied by all conversion results ...
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... If it takes place in association with an internal full-scale calibration, then this system zero-scale calibration should be performed after the full-scale calibration. REV. A AD7730/AD7730L System Full-Scale Calibration A system full-scale calibration is initiated on the AD7730 by writing the appropriate values ( the MD2, MD1 and MD0 bits of the Mode Register ...
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... AD7730/AD7730L The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8 FS and a maximum value of 2.1 FS. However, the span (which is the difference between the bottom of the AD7730’s input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage ...
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... D0 and D1 of the Mode Register. It gives the user access to two digital port pins which can be programmed over the normal serial interface of the AD7730. The two outputs obtain their supply voltage from AV thus the outputs operate levels even in cases where –33– AD7730/AD7730L , DD ...
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... AD7730/AD7730L POWER SUPPLIES There is no specific power sequence required for the AD7730, either the AV or the DV supply can come up first. While DD DD the latch-up performance of the AD7730 is very good important that power is applied to the AD7730 before signals at REF IN, AIN or the logic input pins in order to avoid latch-up caused by excessive current ...
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... CS input is tied low perma- nently. In this case, the SCLK line should idle high between REV. A AD7730/AD7730L data transfer when the POL input is high and should idle low between data transfers when the POL input is low. For POL = 1, the first falling edge of SCLK clocks data from the microcontrol- ler onto the DIN line of the AD7730 ...
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... AD7730/AD7730L In DSP applications, the SCLK is generally a continuous clock. In these applications, the CS input for the AD7730 is generated from a frame synchronization signal from the DSP. In these applications, the first edge after CS goes low is the active edge. The MSB of the data to be shifted into the DSP must be set up prior to this first active edge ...
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... Read From Data Register*/ /* Ensures Part is not Reset While in Continuous Read Mode*/ /* Wait for RDY pin to go low to Indicate Output Update*/ /* Read Conversion Result from AD7730's Data Register*/ /* Ends Continuous Read Operation and Places Part in Mode Where It Expects Write to Communications Register*/ –37– AD7730/AD7730L ...
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... AD7730/AD7730L MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7730’s flexible serial interface allows for easy interface to most microcomputers and microprocessors. The pseudo-code of Table XIX and Table XX outline typical sequences for inter- facing a microcontroller or microprocessor to the AD7730. Figures 20, 21 and 22 show some typical interface circuits. ...
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... The serial clock rate on the ADSP-2105 should be lim- SYNC ited to 3 MHz to ensure correct operation with the AD7730. RESET AD7730 POL DATA OUT DATA IN SCLK ADSP-2105 CS Figure 22. AD7730 to ADSP-2105 Interface –39– AD7730/AD7730L DV DD SYNC RESET AD7730 RFS CS TFS DR DATA OUT DT DATA IN ...
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... AD7730/AD7730L APPLICATIONS The on-chip PGA allows the AD7730 to handle analog input voltage ranges as low full scale. This allows the user to connect a transducer directly to the input of the AD7730. The AD7730 is primarily targeted for weigh-scale and load-cell applications. The majority of the applications have a strain- gage transducer whose resistance changes when subjected to mechanical stress ...
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... PGA +/– AIN2(+)/D1 6-BIT AIN2(–)/D0 SERIAL INTERFACE DAC AND CONTROL LOGIC MICROCONTROLLER ACX AC EXCITATION ACX CLOCK AGND DGND –41– AD7730/AD7730L AD7730 SIGMA-DELTA A/D CONVERTER STANDBY SIGMA- PROGRAMMABLE SYNC DELTA DIGITAL MODULATOR FILTER MCLK IN CLOCK GENERATION MCLK OUT REGISTER BANK SCLK ...
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... AD7730/AD7730L Bipolar Excitation of the Bridge As mentioned previously, some applications will require that the AD7730 handle inputs from a bridge that is excited by a bipolar voltage. The number of applications requiring this are limited, but with the addition of some external components the AD7730 is capable of handling such signals. Figure 25 outlines one ap- proach to the problem ...
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... APPENDIX A AD7730L SPECIFICATIONS –43– ...
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... ACX *Protected by U.S. Patent No: 5, 134, 401. Other Patent Applications Filed. GENERAL DESCRIPTION The AD7730L is a complete low power analog front-end for weigh-scale and pressure measurement applications. The device accepts low level signals directly from a transducer and outputs a serial digital word. The input signal is applied to a proprietary programmable gain front end based around an analog modula- tor ...
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... max DD 0.3 V min 0.65 V max –45– AD7730/AD7730L unless otherwise noted.) Conditions/Comments Offset Error and Offset Drift Refer to Both Unipolar Offset and Bipolar Zero Errors Measured with Zero Differential Voltage At DC. Measured with Zero Differential Voltage 10 SKIP = 0 Offset Error and Offset Drift Refer to Both ...
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... AD7730/AD7730L Parameter LOGIC INPUTS Input Current All Inputs Except SCLK and MCLK Input Low Voltage INL V , Input Low Voltage INL V , Input High Voltage INH SCLK Only (Schmitt Trigerred Input T– V T– V – T– V – T– ...
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... Data Valid to SCLK Edge Setup Time ns min Data Valid to SCLK Edge Hold Time ns min SCLK High Pulsewidth ns min SCLK Low Pulsewidth CS Rising Edge to SCLK Edge Hold Time ns min –47– AD7730/AD7730L CLK IN unless otherwise noted and timed from a voltage level of 1 limits. ...
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... Output Noise (CHP = 0) Table XXIII shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730L when used in nonchopping mode (CHP of Filter Register = 0) with a master clock frequency of 2.4576 MHz. These numbers are typical and are generated at a differential analog input voltage ...
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... Peak-to-Peak Resolution in Counts (Bits) Settling Time Input Range Fast Mode = 80 mV 53.2 ms 85k (16. 82k (16.5) 26.6 ms 65k (16) 13.3 ms 45k (15.5) 6.63 ms 30k (15) –49– AD7730/AD7730L Input Range Input Range Input Range = 215 135 100 245 160 110 275 180 130 370 ...
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... MICROCOMPUTER/MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AD7730 to 68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 38 AD7730 to 8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 38 AD7730 to ADSP-2105 Interface . . . . . . . . . . . . . . . . . . 39 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC Excitation of Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AC Excitation of Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Bipolar Excitation of Bridge . . . . . . . . . . . . . . . . . . . . . . . 42 APPENDIX A–AD7730L SPECIFICATIONS . . . . . . . . . . 43 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 51 TABLE INDEX Table Title Table I. Output Noise vs. Input Range and Update Rate (CHP = 1) Table II ...
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... Thin Shrink Small Outline (RU-24) 0.311 (7.90) 0.303 (7.70 PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) BSC 0.0075 (0.19) 0.0035 (0.090) –51– AD7730/AD7730L 0.325 (8.25) 0.195 (4.95) 0.300 (7.62) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.0291 (0.74) x 45° 0.0098 (0.25) 0.0500 (1.27) 8° 0° 0.0157 (0.40) 0.028 (0.70) 8° 0° 0.020 (0.50) ...
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