CS8406-CZZ Cirrus Logic Inc, CS8406-CZZ Datasheet
CS8406-CZZ
Specifications of CS8406-CZZ
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CS8406-CZZ Summary of contents
Page 1
... For systems with no microcontroller, a Stand-Alone Mode allows di- rect access to channel status and user bit data pins. The CS8406 is available in 28-pin TSSOP, SOIC, and QFN packages in both Commercial (-10º to +70ºC) and Automotive grades (-40º to +85ºC). The CDB8416 Demonstration board is also available for device evaluation and implementation suggestions ...
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... Channel Status Data Buffer Control (12h) .................................................................................. 23 8.14 User Data Buffer Control (13h) ................................................................................................... 24 8.15 Channel Status Bit or User Bit Data Buffer (20h - 37h) .............................................................. 24 8.16 CS8406 I.D. and Version Register (7Fh) (Read Only) ................................................................ 24 9. PIN DESCRIPTION - SOFTWARE MODE ........................................................................................ 25 10. HARDWARE MODE .......................................................................................................................... 28 10.1 Channel Status, User and Validity Data ..................................................................................... 28 10 ...
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... LIST OF TABLES Table 1. Control Register Map Summary................................................................................................... 18 Table 2. Hardware Mode COPY/C and ORIG Pin Functions..................................................................... 29 Table 3. Hardware Mode Serial Audio Port Format Selection ................................................................... 29 Table 4. Hardware Mode OMCK Clock Ratio Selection............................................................................. 29 Table 5. Equivalent Register Settings of Serial Audio Input Formats in Hardware Mode .......................... 29 DS580F5 CS8406 3 ...
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... T A Automotive Grade T A Symbol VD, VL (Note stg Symbol 5.0 V (Note 5.0 V CS8406 Min Typ Max 3.14 3.3 or 5.0 5.25 3.14 3.3 or 5.0 5.25 -10 - +70 -40 - +85 Min Max - 6.0 - ±10 -0 0.3 -55 125 -65 150 Min Typ Max ...
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... Frame Rate AES3 Transmitter Output Jitter DS580F5 Symbol I in Symbol ( 5 3 5 3.3 V Symbol pF) L Symbol CS8406 Min Typ Max Units - - ±0.5 - 0.25 - Min Max Units 0.7 - 0.7 2. 0.3 2 0.3 -0.3 0.8 -0.3 0.8 ...
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... L Symbol (Note (Note (Note 5) t smd (Note 6) t lmd t sckw t sckl t sckh (Note 7) t lrckd (Note 8) t lrcks ILRCK (input) t lrckd ISCLK (input) lmd SDIN Figure 2. Audio Port Slave Mode and Data Input Timing CS8406 Min Typ Max Units 14 14 ...
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... CS t css CCLK t r2 CDIN CDOUT DS580F5 = 20 pF) L Symbol (Note 9) f sck t csh t css t scl (Note 10) t sch t dsu (Note 11 (Note 12 (Note 12 scl t sch dsu Figure 3. SPI Mode Timing CS8406 Min Typ Max Units 0 - 6.0 MHz μs 1 MAX ((1/256 F + 8), 66 ...
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... SCL t low pF) L Symbol fscl t buf t hdst t low t high t sust (Note 13) t hdd t sud susp Repeated Start t high t t sud t sust hdd Figure 4. I²C Mode Timing CS8406 Min Typ Max Units - - 100 kHz μs 4 μs 4 μs 4 μs 4 μs 4 μ 250 - - ns ...
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... Figure 5. Recommended Connection Diagram for Software Mode DS580F5 μ 0 RXP ILRCK TXP CS8406 ISCLK TXN SDIN OMCK AD0 / CS AD1 / CDIN AD2 SCL / CCLK SDA / CDOUT H/S RST INT TCBL GND CS8406 +3 +5.0 V μ 0.1 F Transmission Interface User Data U Source 47kΩ 9 ...
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... VD VL H/S ILRCK ISCLK SDIN TXP CS8406 TXN OMCK COPY/C HWCK1 HWCK0 SFMT0 SFMT1 APMS TCBLD RST CEN EMPH AUDIO ORIG TCBL GND CS8406 +3 +5.0 V μ 0.1 F Transmission Interface C Data Source User Data U Source 47kΩ Validity V Source 47kΩ DS580F5 ...
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... GENERAL DESCRIPTION The CS8406 is a monolithic CMOS device which encodes and transmits audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8406 accepts audio, channel status and user da- ta, which is then multiplexed, encoded, and driven onto a cable. ...
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... See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit 12 Right Left MSB LSB MSB Left Right LSB MSB MSB Left MSB LSB SISF* SIRES[1:0]* SIJUST Figure 7. Serial Audio Input Example Formats CS8406 LSB MSB LSB MSB Right MSB LSB SIDEL* SISPOL* SILRPOL DS580F5 ...
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... The channel status (C) and user (U) bits in the transmitted data stream are taken from storage areas within the CS8406. The user can access the internal storage or configure the CS8406 to run in one of several automatic modes. ...
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... OMCKS if TCBL is an input th Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data, Stereo Mode 14 Figure 8 Thold VCU[1] VCU[2] Data [5] Data [6] Data [1] X Data [2] Y CS8406 and Figure 9. VLRCK is the internal vir- VCU[3] VCU[4] Data [7] Data [8] Data [3] X Data [4] DS580F5 ...
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... AES3 frame rate 1. T setup hold 3. T > 3 OMCKS if TCBL is an input th Figure 9. AES3 Transmitter Timing for C, U, and V Pin Input Data, Mono Mode DS580F5 U[0] Data [5] Data [6] Y Data [2]* Y Data [3]* CS8406 U[2] Data [7] Data [8] X Data [4]* X Data [5]* 15 ...
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... However, to avoid potential interference problems, the control port pins should remain static if no op- eration is required. The control port has two modes: SPI and I²C, with the CS8406 acting as a slave device. SPI Mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C Mode is selected by connecting the AD0/CS pin through a resistor GND, thereby permanently selecting the desired AD0 bit address state ...
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... MAP will be output. The MAP automatically increments, so consecutive registers can read from or written to easily. Each byte is separated by an acknowledge bit (ACK). The ACK bit is output from the CS8406 after each input byte is read, and is input to the CS8406 from the microcontroller after each transmitted byte. ...
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... CS Data Buffer Control 13 U Data Buffer Control 1D-1F Reserved 20- Data Buffer 7F ID and Version Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8406 ...
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... MMT - Select AES3 transmitter mono or stereo operation Default = ‘0’ Normal stereo operation 1 - Output either left or right channel inputs into consecutive subframe outputs (Mono Mode, left or right is determined by MMTLR bit) DS580F5 MAP4 MAP3 MUTEAES CS8406 MAP2 MAP1 MAP0 INT1 INT0 TCBLD MMT MMTCS MMTLR 19 ...
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... Reading and writing the U and C data buffers is not possible. Power consumption is low Normal part operation. This bit must be set allow the CS8406 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. ...
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... SDIN sampled on rising edges of ISCLK 1 - SDIN sampled on falling edges of ISCLK SILRPOL - ILRCK clock polarity Default = ‘0’ SDIN data is for the left channel when ILRCK is high 1 - SDIN data is for the right channel when ILRCK is high DS580F5 SIRES0 SIJUST CS8406 SIDEL SISPOL SILRPOL 21 ...
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... INT pin and the status register mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in Interrupt 1 register. This register defaults to 00h CS8406 EFTC EFTU EFTCM 0 DS580F5 ...
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... BSEL - Selects the data buffer register addresses to contain User data or Channel Status data Default = ‘0’ Data buffer address space contains Channel Status data 1 - Data buffer address space contains User data DS580F5 CS8406 EFTC1 0 0 EFTC0 EFTUM EFTU1 0 0 EFTU0 EFTCI CAM 0 23 ...
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... Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to Block Mode) is accessible through these register addresses. 8.16 CS8406 I.D. and Version Register (7Fh) (Read Only ID3 ID2 ID[3: code for the CS8406. Permanently set to 1110 VER[3:0] = 0001 (revision A) VER[3:0] = 0010 (revision ...
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... SDIN SDA / CDOUT AD0 / CS AD2 RXP TSTN VD TEST DS580F5 Thermal Pad 5 6 Top-Down (Through Package) View 28-Pin QFN Package CS8406 SCL / CCLK 28 AD1 / CDIN 27 TXP 26 TXN 25 H GND 22 OMCK INT 19 TEST 18 TEST 17 TEST 16 TCBL 15 OMCK INT 19 TEST 18 TEST 17 TEST 16 TCBL 15 25 ...
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... Ground (Input) - Ground for I/O and core logic. Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are sta- ...
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... Test Pins - These pins are unused inputs recommended that these pins be tied to a supply (VL or TEST 11 GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how- ever current consumption from VL will increase by 25 μA per TEST pin that is left floating. 16 ...
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... MODE The CS8406 has a Hardware Mode that allows the use of the device without a microcontroller. Hardware Mode is selected by connecting the H/S pin to VL. The flexibility of the CS8406 is necessarily limited in Hardware Mode. Various pins change function as described in the Hardware Mode pin description section. ...
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... Serial Input Format IF3 - Right-Justified, 24-bit data 1 Serial Input Format IF4 - Right-Justified, 16-bit data Function 0 0 OMCK Frequency is 256* OMCK Frequency is 128* OMCK Frequency is 512* OMCK Frequency is 256*Fs SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL CS8406 Table 3, and may be set to master or slave Table 4. Table 5 describes ...
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... TEST RST APMS TCBLD ILRCK ISCLK SDIN COPY / C TEST EMPH SFMT0 SFMT1 VD TEST Thermal Pad 5 6 Top-Down (Through Package) View 28-Pin QFN Package CS8406 ORIG 28 HWCK1 27 TXP 26 TXN 25 H GND 22 OMCK 21 HWCK0 20 AUDIO CEN 16 TCBL 15 OMCK 21 HWCK0 20 AUDIO CEN 16 TCBL 15 DS580F5 ...
Page 31
... Ground (Input) - Ground for I/O and core logic. Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable ...
Page 32
... Test Pins (Input) - These pins are unused inputs recommended that these pins be tied to a supply TEST 7 (VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left float- ing, however current consumption from VL will increase by 25 μA per TEST pin that is left floating. 8 Thermal Pad (QFN package only) - Thermal relief pad for optimized heat dissipation ...
Page 33
... Power Supply, Grounding, and PCB layout The CS8406 operates from +3 +5.0 V and +5.0 V supply. These supplied may be set independently. Follow normal supply decoupling practices, see plies should be decoupled with a 0.1 μ F capacitor to GND to minimize AES3 transmitter induced transients. ...
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... JEDEC #: MS-013 Controlling Dimension is Millimeters CS8406 MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.42 0.51 0.23 0.28 ...
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... BSC 9.60 BSC 0.256 6.30 0.177 4. 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS8406 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 2,3 9.70 BSC 9.80 BSC 6 ...
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... MIN 0.03937 0.800 0.001969 0.000 0.009843 0.150 -- -- 0.161417 3.900 0.106299 2.500 0.161417 3.900 0.106299 2.500 0.019685 0.300 JEDEC #: MO-220 Controlling Dimension is Millimeters. CS8406 b e PIN #1 CORNER D2 L BOTTOM VIEW MILLIMETERS NOTE NOM MAX 0.900 1.000 0.020 0.050 0.200 0.250 0.400 -- 4.000 4 ...
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... CS8406 Container Order# Rail CS8406-CSZ Tape and Reel CS8406-CSZR Rail CS8406-DSZ Tape and Reel CS8406-DSZR Rail CS8406-CZZ Tape and Reel CS8406-CZZR Rail CS8406-DZZ Tape and Reel CS8406-DZZR Rail CS8406-CNZ Tape and Reel CS8406-CNZR Rail CS8406-DNZ Tape and Reel CS8406-DNZR - - CDB8416 ...
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... AES3 Transmitter External Components The output drivers on the CS8406 are designed to drive both the professional and consumer interfaces. The AES3 and IEC60958-4 specifications call for a balanced output drive of 2-7 V peak-to-peak into a 110 Ω ± 20% load with no cable attached. Using the circuit in protected, has the proper source impedance, and provides peak-to-peak signal into a 110 Ω ...
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... A flowchart for reading and writing to the E buffer is shown in after transfer, which is based on the output timebase. If the channel status block to transmit indicates PRO Mode, then the CRCC byte is automatically calcu- lated by the CS8406, and does not have to be written into the last byte of the block by the host microcon- DS580F5 A ...
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... When reading data in One-Byte Mode, a single byte is returned, which can be from channel data, depending on a register control bit write is being done, the CS8406 expects a single byte to be input to its control port. This byte will be written to both the A and B locations in the addressed word. ...
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... In these situations, Two-Byte Mode should be used to access the E buffer. In this mode, a read will cause the CS8406 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be input to the CS8406's control port. The A channel status data is first ...
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... Description - Software Mode” on page “General Description” on page 34, and “Ordering Information” on page and “Pin Description - Hardware Mode” on page “Power Supply, Grounding, and PCB layout” on 33. www.cirrus.com CS8406 “Table of “Control Port Description” on 25. 1, “Package Dimen- 37. “Pin Description - Software 30. ...