AD9739 Analog Devices, AD9739 Datasheet

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AD9739

Manufacturer Part Number
AD9739
Description
14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9739

Resolution (bits)
14bit
Dac Update Rate
2.5GSPS
Dac Settling Time
n/a
Max Pos Supply (v)
+3.5V
Single-supply
Yes
Dac Type
Current Out
Dac Input Format
LVDS,Par

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Data Sheet
FEATURES
Direct RF synthesis at 2.5 GSPS update rate
Industry leading single/multicarrier IF or RF synthesis
Dual-port LVDS data interface
Pin-compatible with the
Multichip synchronization capability
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.16 W at 2.5 GSPS
APPLICATIONS
Broadband communications systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The
to-analog converter (DAC) capable of synthesizing wideband
signals from dc up to 3.0 GHz. Its DAC core features a quad-
switch architecture that provides exceptionally low distortion
performance with an industry-leading direct RF synthesis
capability. This feature enables multicarrier generation up to
the Nyquist frequency in baseband mode as well as second and
third Nyquist zones in mix mode. The output current can be
programmed over the 8.66 mA to 31.66 mA range.
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. Multichip synchronization is possible
with an on-chip synchronization controller. A serial peripheral
interface (SPI) is used for device configuration as well as readback
of status registers.
The
operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball
chip scale ball grid array for reduced package parasitics.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix mode
f
f
f
Up to 1.25 GSPS operation
Source synchronous DDR clocking
OUT
OUT
OUT
AD9739
AD9739
= 350 MHz, ACLR =80 dBc
= 950 MHz, ACLR = 78 dBc
= 2100 MHz, ACLR = 69 dBc
is a 14-bit, 2.5 GSPS high performance RF digital-
is manufactured on a 0.18 μm CMOS process and
AD9739A
RF Digital-to-Analog Converter
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
SYNC_OUT
SYNC_IN
Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix
mode operation.
A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
On-chip controllers manage external and internal clock
domain skews.
A multichip synchronization capability.
Programmable differential current output with a 8.66 mA
to 31.66 mA range.
SCLK
SDIO
SDO
DCO
DCI
CS
FUNCTIONAL BLOCK DIAGRAM
CLK DISTRIBUTION
CONTROLLER
©2009–2012 Analog Devices, Inc. All rights reserved.
RESET
SPI
SYNC-
(DIV-BY-4)
14-Bit, 2.5 GSPS,
Figure 1.
AD9739

IRQ
DAC BIAS
DACCLK
TxDAC
CORE
1.2V
AD9739
www.analog.com
VREF
I120
IOUTP
IOUTN

Related parts for AD9739

AD9739 Summary of contents

Page 1

... A multichip synchronization capability. 6. Programmable differential current output with a 8. 31.66 mA range. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved. AD9739 1.2V VREF I120 IOUTP TxDAC CORE IOUTN DACCLK www.analog.com ...

Page 2

... Analog Modes of Operation ..................................................... 38   Clock Input Considerations...................................................... 39   Voltage Reference ....................................................................... 40   Analog Outputs .......................................................................... 40   Nonideal Spectral Artifacts....................................................... 43   Lab Evaluation of the AD9739 ................................................. 44   Power Dissipation and Supply Domains................................. 44   Recommended Start-Up Sequence .......................................... 45   Outline Dimensions ....................................................................... 48   Ordering Guide .......................................................................... 48   ) and Sleep ........... 23 OUTFS   ...

Page 3

... Deleted Clocking the AD9739 Section, Figure 85, and Figure 86..39 Added Clock Input Considerations Section, Figure 58 to Figure 60...........................................................................................39 Deleted Clock Phase Noise Affects on AC Performance Section, Table 32 to Table 34, Applying Data to the AD9739 Section, and Figure 87...........................................................................................40 Moved Figure 61..............................................................................40 Changes to Voltage References Section and Analog Outputs ...

Page 4

... AD9739 SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1 Table 1. Parameter RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ANALOG OUTPUTS Gain Error (with Internal Reference) Full-Scale Output Current Output Compliance Range Common-Mode Output Resistance Differential Output Resistance Output Capacitance DAC CLOCK INPUT (DACCLK_P, DACCLK_N) ...

Page 5

... Max 825 1575 175 400 −175 −400 80 120 1.2 1250 344 825 1575 175 400 −175 −400 80 120 1.2 625 1375 1025 150 200 250 1150 1250 80 100 120 10 625 AD9739 Unit Ω pF MSPS Ω pF MHz Ω % MHz ...

Page 6

... AD9739 SERIAL PORT SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V. Table 3 . Parameter WRITE OPERATION (See Figure 36) SCLK Clock Rate SCLK SCLK SCLK Clock High SCLK Clock Low, t LOW SDIO to SCLK Setup Time SCLK to SDIO Hold Time SCLK Setup Time, t ...

Page 7

... MSPS. DAC DAC = 20 mA 2400 MSPS. OUTFS DAC = f + 1.25 MHz OUT2 OUT1 divided by the minimum required interpolation factor. For the AD9739, the minimum interpolation factor is 1. Thus, Rev Page AD9739 Min Typ Max Unit 800 2500 MSPS 800 2500 ...

Page 8

... AD9739 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To VDDA VSSA VDD33 VSS VDD VSS VDDC VSSC VSSA VSS VSSA VSSC VSS VSSC DACCLK_P, DACCLK_N VSSC DCI, DCO, SYNC_IN, VSS SYNC_OUT LVDS Data Inputs VSS IOUTP, IOUTN VSSA I120, VREF VSSA IRQ, CS, SCLK, SDO, ...

Page 9

... VDDC, 1.8V, CLOCK SUPPLY VSSC, CLOCK SUPPLY GROUND Figure 4. Digital LVDS Clock Supply Pins (Top View Figure 5. Digital LVDS Input, Clock I/O (Top View) AD9739 14 DCO_P/_N DCI_P/_N ...

Page 10

... Table 7. AD9739 Pin Function Descriptions Pin No. C1, C2, D1, D2, E1, E2, E3, E4 A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 A12, A13, B12, B13, C12, C13, D12, D13, A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3, ...

Page 11

... Port 0 Positive/Negative Data Input Bit 8. DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10. DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11. DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12. DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13. Rev Page AD9739 ...

Page 12

... AD9739 TYPICAL PERFORMANCE CHARACTERISTICS AC (NORMAL MODE mA, nominal supplies, 25°C, unless otherwise noted. OUTFS START 20MHz VBW 10kHz Figure 7. Single-Tone Spectrum MHz, f OUT 80 1.2GSPS 1.6GSPS 2.4GSPS 55 2.0GSPS 100 200 300 400 500 600 700 800 900 1000 1100 1200 ...

Page 13

... OUT vs. Digital Full Scale OUT 20mA 10mA FS 60 30mA 100 200 300 400 500 600 700 f (MHz) OUT Figure 18. IMD vs. f over DAC I OUT OUTFS AD9739 0dBFS 800 900 1000 –3dBFS 800 900 1000 800 900 1000 ...

Page 14

... AD9739 –40°C 60 +25° 100 200 300 400 500 600 f (MHz) OUT Figure 19. SFDR vs. f over Temperature OUT –150 –152 –154 –156 –158 –160 –162 +85°C –164 –166 +25°C –168 –170 0 100 200 300 400 500 600 ...

Page 15

... FIRST ADJ CH –65 –70 SECOND ADJ CH –75 FIFTH ADJ CH –80 –85 –90 1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686 f (MHz) OUT Figure 30. Single-Carrier WCDMA ACLR vs. f OUT AD9739 STOP 2.4GHz STOP 2.4GHz = 1.31 GHz, OUT at 2457.6 MSPS ...

Page 16

... AD9739 CENTER 2.807GHz #RES BW 30kHz SWEEP 174.6ms (601pts) VBW 300kHz FREQ REF RMS RESULTS OFFSET BW LOWER CARRIER POWER (MHz) (MHz) (dBc) (dBm) 5 3.84 –64.90 –89.30 –24.4dBm/ 10 3.84 –66.27 –90.67 3.84MHz 15 3.84 –68.44 –92.84 20 3.84 –70.20 –94.60 25 3.84 –70.85 –95.25 Figure 31. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz 2457 ...

Page 17

... Intermodulation Distortion (IMD) . For offset and gain IMD is the result of two or more signals at different frequencies mixing together. Many products are created according to the formula, aF1 ± bF2, where a and b are integer values. Rev Page AD9739 ...

Page 18

... A SPI initialization routine is required as part of the boot process. See Table 31 and Table 32 for example procedures. Reset Issuing a hardware or software reset places the AD9739 SPI registers in a known state. All SPI registers (excluding 0x00) are set to their default states as described in Table 10 upon issuing a reset ...

Page 19

... R/W Figure 37. SPI 3-Wire Read Operation Timing SCLK t t LOW R Figure 38. SPI 4-Wire Read Operation Timing Rev Page AD9739 ...

Page 20

... AD9739 SPI REGISTER MAP Table 9. Full Register Map (N/A = Not Applicable) Hex Name Addr Bit 7 Bit 6 Mode 00 SDIO_DIR LSB/MSB Power- 01 N/A N/A Down CNT_ 02 N/A N/A CLK_DIS IRQ_EN 03 N/A N/A IRQ_REQ 04 N/A N/A RSVD 05 N/A N/A FSC_1 06 FSC[7] FSC[6] FSC_2 07 Sleep N/A DEC_ 08 N/A N/A CNT RSVD 09 N/A N/A LVDS_ 0A N/A N/A CNT DIG_ 0B HNDOFF_ HNDOFF_ STAT Fall[3] Fall[2] ...

Page 21

... SRCH_MODE SET_PHS[4] SET_PHS[3] [0] MUDEL[6] MUDEL[5] MUDEL[4] CONTRST Guard[4] Guard[3] N/A N/A N/A N/A N/A N/A N/A N/A N/A HDRM[5] HDRM[4] HDRM[3] N/A N/A N/A N/A N/A N/A ID[5] ID[4] ID[3] Rev Page AD9739 Bit 2 Bit 1 Bit 0 SYNCOUT CLKDIV CLKDIV PH[0] PH[1] PH[0] DCI_ DCI_ DCI_ DEL[4] DEL[3] DEL[2] FINE_DEL_ FINE_DEL_ FINE_DEL_ PRE[2] PRE[1] PRE[0] SYNCO_ SYNCO_ SYNCO_ DEL[2] DEL[1] DEL[0] N/A N/A N/A SYNCSH_ ...

Page 22

... AD9739 SPI PORT CONFIGURATION AND SOFTWARE RESET Table 10. SPI Port Configuration and Software Reset Register Address Default (Hex) Setting Name Bit R/W 0x00 SDIO_DIR 7 R/W 0 LSB/MSB 6 R/W 0 Reset 5 R/W 0 POWER-DOWN LVDS INTERFACE AND TXDAC® Table 11. Power-Down LVDS Interface and TxDAC Register ...

Page 23

... When enabled, the data receiver controller generates an IRQ; it falls out of lock and automatically begins a search/track routine. 0 Data receiver controller enabled disable enable. Rev Page Comments 0x00 = normal baseband mode. 0x01 = return-to-zero mode. 0x02 = mix mode. AD9739 ...

Page 24

... AD9739 DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE Table 19. Data Receiver Controller_Data Sample Delay Value Register Address (Hex) Name Bit R/W 0x11 SMP_DEL[1:0] [7:6] R/W 0x12 SMP_DEL[9:2] [7:0] R/W DATA AND SYNC RECEIVER CONTROLLER_DCI DELAY VALUE/WINDOW AND PHASE ROTATION Table 20. Data and Sync Receiver Controller_DCI Delay Value/Window and Phase Rotation Register ...

Page 25

... Sets the direction in which the mu controller searches (from its initial MUDEL setting) for the optimum mu delay line setting that corresponds to the desired phase/slope setting (that is, SET_PHS and slope ). 00 = down up down/up (recommended). 0 Sets the target phase that the mu controller locks to with a maximum setting of 16. Refer to Table 28 for optimum setting. Rev Page AD9739 ...

Page 26

... AD9739 Address (Hex) Name Bit R/W 0x28 MUDEL[8:1] [7: 0x29 SEARCH_TOL 7 R/W Retry 6 R/W CONTRST 5 R/W Guard[4:0] 4 R/W 0x2A MU_LST 1 R MU_LKD 0 R PART ID Table 25. Part ID Register Address (Hex) Name 0x35 PART_ID Default Setting Comments 0x00 With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the value that the mu delay is set to ...

Page 27

... Data Sheet THEORY OF OPERATION Figure 39 shows a top-level functional diagram of the AD9739. A high performance TxDAC core delivers a signal dependent, differential current (nominal ±10 mA balanced load referenced to ground. The frequency of the clock signal appearing at the AD9739 differential clock receiver, DACCLK, sets the TxDAC’s update rate. This clock signal, which serves as ...

Page 28

... The delay line within the data receiver DIV-BY-4 DAC controller can track a ±1.5 ns skew variation after initial lock. While it is possible for the host to have an internal PLL that AD9739 and generates a synchronous f derived, digital implementations that result in the shortest propagation delays result in the lowest skew variation. ...

Page 29

... Rev Page DCI FROM SYNC CONTROLLER DELAY OR PATH SPI REG 0x14, BIT[7:6] PHASE ROTATION 0 90 DIV-BY-4 180 270 TO SYNC SAMPLE CONTROLLER DELAY PATH DATA TO CORE DDR FF DIV-BY-4 DCI PST PRE FINE_DEL_SKEW Figure 43. Pre- and Post-Delay Sampling Diagram AD9739 F DAC ...

Page 30

... Upon initialization of the AD9739, a certain period of time is required for the data receiver controller to lock onto the DCI clock signal. Note that, due to its dependency on the mu controller and ...

Page 31

... LVDS_2 LVDS_N 100Ω 1. 4.75 × 100 2.50 × 100/N Figure 47. Resistor Network to Bias Unused LVDS Data Inputs LVDS inputs do not include fail-safe capability. of 1.4 V and 1.0 V, respectively, depending on the N Logic Bit Binary Equivalent AD9739 LVDS RECEIVER 1.4V 1.0V 0.4V 0V –0.4V LOGIC 1 LOGIC 0 ...

Page 32

... Clock Rate (GSPS) 0.8 0.9 1.0 320 360 400 440 1.1 1.2 1.3 1.4 1.5 1.6 to 2.5 Rev Page Data Sheet NOM_P1 SLOW_P1 FAST_P1 120 160 200 240 280 320 360 DELAY LINE TAP Lots at 1.2 GSPS AD9739 based on the Slope MU Phase − 6 − − 12 − 10 − 8 − 6 400 440 ...

Page 33

... Bit 3). Once the read bit is set, the MUDEL[8:0] bits and the SET_PHS[4:0] bits (Register 0x27 and Register 0x28) that the controller is currently using can be read. Rev Page AD9739 ...

Page 34

... Table 29. Interrupt Request Registers Address (Hex) 0x03 0x04 0x21 (PIN F13) INT SOURCE SPI ISR READ DATA 0x2A SPI WRITE SPI ADDRESS DATA = 1 Rev Page Data Sheet AD9739 initialization Bit Description 5 SYNC_LST_EN 4 SYNC_LCK_EN 3 MU_LST_EN 2 MU_LCK_EN 1 RCV_LST_EN 0 RCV_LCK_EN 5 SYNC_LST_IRQ ...

Page 35

... Figure 53). This phase ambiguity can result in a ±2 sample offset between any two devices. Because the state of this internal divider is unknown at power-up, a synchronization method that phase aligns the digital paths of multiple AD9739s is required to ensure matching pipeline delays. Figure 52 shows a top-level diagram of multiple AD9739s ...

Page 36

... Figure 53. Top Level Block Diagram of Synchronization Circuitry and Controller Figure 53 shows a top-level diagram of the synchronization controller (bottom) and how it interfaces to other digital functional blocks within the AD9739. Note the following observations of this top level diagram: • Synchronization between multiple devices is achieved by rotating the div-by-4 phases of the slave devices such that they align with the master ...

Page 37

... DCI outputs. Adding to this dilemma is that it also possible for the data receiver controller of different AD9739s to converge on different delay settings due to PVT variations of the delay line (even if DCI inputs are exactly aligned). This can result in a four sample ...

Page 38

... DACCLK edge, while the other half change state on the falling DACCLK edge. DACCLK_x CLK LATCHES DBx[13: IOUTP Figure 54. AD9739 Quad-Switch Architecture INPUT DATA DACCLK_x TWO-SWITCH ...

Page 39

... PMOS IOUT ARRAY CLKx_OFFSET DIR_x = 0 DACCLK_P ESD DACCLK_N CLKx_OFFSET DIR_x = 0 4-BIT NMOS IOUT ARRAY Figure 58. Clock Input and Common-Mode Control clock receiver features the ability to independently AD9739 50Ω 50Ω 1nF Q DACCLK_P 100Ω Q DACCLK_N 1nF CLK Input AD9739 3.9nH 1nF DACCLK_P 100Ω ...

Page 40

... ANALOG OUTPUTS Equivalent DAC Output and Transfer Function The AD9739 and IOUTN, that source current into an external ground reference load. Figure 63 shows an equivalent output circuit for the DAC ...

Page 41

... PEAK AD9739 R SOURCE = 50Ω 8.6 – 31.2mA OUTFS = AC 70Ω 180Ω Rev Page programmed for mA, its peak ac OUTFS 2 R). Because the source and load , although any degradation in OUTFS LOSSLESS R BALUN LOAD = 50Ω 1:1 AD9739 ...

Page 42

... Any imbalance in the output impedance between the IOUTP and IOUTN pins results in asymmetrical signal swings that degrade the distortion performance (mostly even order) and noise performance. Component selection and layout are critical in realizing the performance potential of the AD9739. MINI-CIRCUITS IOUTP 90Ω 70Ω ...

Page 43

... DAC ¾ × Rev Page Images appear as replicas of the original signal, therefore, can be easier to identify. In the case of the AD9739, internal modulation of the sampling clock at intervals related generate image pairs at ¼ × ½ × f DAC DAC Both upper and lower sideband images associated with ¼ × ...

Page 44

... LAB EVALUATION OF THE AD9739 Figure 72 shows a recommended lab setup that was used to characterize the performance of the AD9739. The DPG2 is a dual port LVDS/CMOS data pattern generator available from Analog Devices, Inc., with 1.25 GSPS data rate. The DPG2 directly interfaces to the AD9739 Tyco Z-PACK HM-Zd connectors ...

Page 45

... Data Sheet RECOMMENDED START-UP SEQUENCE Upon power-up of the AD9739, a host processor is required to initialize and configure the AD9739 via its SPI port. Figure 75 shows a flowchart of the sequential steps required, while Table 31 and Table 32 provides more detail on the SPI register write/read operations required to implement the flowchart steps. Note the following: • ...

Page 46

... not locked, proceed to Step 10 and repeat. Limit attempts to three before breaking out of the loop and reporting a mu lock failure. Ensure that the AD9739 is fed with DCI clock input from the data source. Set FINE_DEL_SKEW to 2. Disable the data Rx controller before enabling it. ...

Page 47

... DCI_DEL value to be average between master and readback DCI_DEL value. Optional: modify the TxDAC I setting (the default is 20 mA). OUTFS Optional: modify the TxDAC operation mode (the default is normal mode). Rev Page AD9739 ...

Page 48

... AD9739BBCZ −40°C to +85°C AD9739BBCZRL −40°C to +85°C AD9739BBC −40°C to +85°C AD9739BBCRL −40°C to +85°C AD9739-R2-EBZ RoHS Compliant Part. ©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...

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