CS8421-CZZ Cirrus Logic Inc, CS8421-CZZ Datasheet

IC SAMPLE RATE CONVERTER 20TSSOP

CS8421-CZZ

Manufacturer Part Number
CS8421-CZZ
Description
IC SAMPLE RATE CONVERTER 20TSSOP
Manufacturer
Cirrus Logic Inc
Type
Sample Rate Converterr
Datasheet

Specifications of CS8421-CZZ

Package / Case
20-TSSOP
Applications
CD-R, DAT, DVD, MD, VTR
Mounting Type
Surface Mount
Operating Supply Voltage
3.3 V / 5.0 V
Operating Temperature Range
- 10 C to + 70 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1018 - BOARD EVAL FOR CS8421
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1126-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS8421-CZZ
Manufacturer:
CIRRUS
Quantity:
1 223
Part Number:
CS8421-CZZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS8421-CZZR
0
Features
MS_SEL
ISCLK
ILRCK
SAOF
175 dB Dynamic Range
–140 dB THD+N
No Programming Required
No External Master Clock Required
Supports Sample Rates up to 211 kHz
Input/Output Sample Rate Ratios of 7.5:1 to 1:8
Master Clock Support for 128 x Fs, 256 x Fs,
384 x Fs, and 512 x Fs (Master Mode)
16-, 20-, 24-, or 32-bit Data I/O
32-bit Internal Signal Processing
Dither Automatically Applied and Scaled to
Output Resolution
Flexible 3-wire Serial Digital Audio Input and
Output Ports
Master and Slave Modes for Both Input and
Output
SDIN
SAIF
http://www.cirrus.com
32-bit, 192-kHz Asynchronous Sample Rate Converter
3.3 V or 5.0 V (VL)
Audio
Serial
Decoder
Input
Serial
Mode
RST
Port
Sync Info
Data
2.5 V (VD)
Varying
Digital
Digital
Filters
Time
Copyright  Cirrus Logic, Inc. 2010
PLL
Level Translators
(All Rights Reserved)
Sync Info
GND
Data
The CS8421 supports sample rates up to 211 kHz and
is available in 20-pin TSSOP and QFN packages in both
Commercial (-10° to +70°C) and Automotive (-40° to
+85°C and -40° to +105°C) grades. The CDB8421 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. See
dering Information” on page 36
Bypass Mode
Time Division Multiplexing (TDM) Mode
Attenuates Clock Jitter
Multiple Device Outputs are Phase Matched
Linear Phase FIR Filter
Automatic Soft Mute/Unmute
+2.5 V Digital Supply (VD)
+3.3 V or 5.0 V Digital Interface (VL)
Space-saving 20-pin TSSOP and QFN
Packages
BYPASS
XTI
Generator
Data
Clock
XTO
Output
Audio
Serial
for complete details.
CS8421
TDM_IN
SDOUT
OSCLK
OLRCK
SRC_UNLOCK
MCLK_OUT
DS641F5
July ‘10
“Or-

Related parts for CS8421-CZZ

CS8421-CZZ Summary of contents

Page 1

... Space-saving 20-pin TSSOP and QFN  Packages The CS8421 supports sample rates up to 211 kHz and is available in 20-pin TSSOP and QFN packages in both Commercial (-10° to +70°C) and Automotive (-40° to +85°C and -40° to +105°C) grades. The CDB8421 Cus- tomer Demonstration board is also available for device evaluation and implementation suggestions ...

Page 2

... Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mix- ing consoles, high-quality D/A, effects processors, computer audio systems, and automotive audio systems. The CS8421 is also suitable for use as an asynchronous decimation or interpolation filter. See Cirrus Logic Appli- cation Note AN270, “Audio A/D Conversion with an Asynchronous Decimation Filter”, available at for more details ...

Page 3

... Data Resolution and Dither .............................................................................................. 20 4.3.2 SRC Locking and Varispeed ............................................................................................ 20 4.3.3 Bypass Mode ................................................................................................................... 20 4.3.4 Muting .............................................................................................................................. 21 4.3.5 Group Delay and Phase Matching Between Multiple CS8421 Parts ............................... 21 4.3.6 Master Clock .................................................................................................................... 21 4.3.7 Clocking ........................................................................................................................... 22 4.4 Time Division Multiplexing (TDM) Mode ....................................................................................... 22 4.5 Reset, Power-Down, and Start-Up ............................................................................................... 23 4 ...

Page 4

... Figure 12. TDM Master Mode Timing Diagram.......................................................................................... 23 Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)....................................................... 23 Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave) .................... 23 Figure 15. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz ..................................... 25 Figure 16. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz ................................ 25 Figure 17 ...

Page 5

... Figure 65. THD+N vs. Frequency Input, 0 dBFS, 44.1 kHz:48 kHz ........................................................... 33 Figure 66. THD+N vs. Frequency Input, 0 dBFS, 96 kHz:48 kHz .............................................................. 33 LIST OF TABLES Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL) ................. 19 Table 2. Serial Audio Input Port Start-Up Options (SAIF) .......................................................................... 19 Table 3. Serial Audio Output Port Start-Up Options (SAOF) ..................................................................... 19 DS641F5 CS8421 5 ...

Page 6

... PIN DESCRIPTIONS 1.1 TSSOP PIN DESCRIPTIONS XTO XTI VD GND RST BYPASS ILRCK ISCLK SDIN MCLK_OUT CS8421 SRC_UNLOCK SAIF SAOF VL GND MS_SEL OLRCK OSCLK SDOUT TDM_IN DS641F5 ...

Page 7

... Digital Power (Input) - Digital core power supply. Typically +2.5 V. GND 4 Ground (Input) - Ground for I/O and core logic. Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are RST 5 reset. On initial power-up, RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase ...

Page 8

... QFN PIN DESCRIPTIONS VD GND RST BYPASS ILRCK Thermal Pad 4 Top-Down View 20-pin QFN Package CS8421 VL 15 GND 14 MS_SEL 13 OLRCK 12 OSCLK 11 DS641F5 ...

Page 9

... GND 2 Ground (Input) - Ground for I/O and core logic. Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are RST 3 reset. On initial power-up, RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase ...

Page 10

... T -10 A ‘-CNZ’ -10 ‘-DZ’ -40 ‘-EZ’ -40 ‘-ENZ’ -40 Symbol Min VD -0.3 VL -0.3 (Note -0 - -65 stg CS8421 Max Units 2.5 2. +70 °C - +70 °C - +85 °C - +105 °C - +105 °C Max Units 3.5 V 6.0 V ±10 mA VL+0.4 ...

Page 11

... A-Weighted - 180 Unweighted - 177 A-Weighted - 175 Unweighted - 172 A-Weighted - 180 Unweighted - 177 A-Weighted - 179 Unweighted - 176 A-Weighted - 176 Unweighted - 173 A-Weighted - 175 Unweighted - 172 - -161 - -171 - -130 - -160 - -148 - -168 - -173 CS8421 Units bits kHz kHz kHz kHz kHz Degrees dBFS - ...

Page 12

... XTI-XTO, in which case the crystal will begin oscillating. 5. Normal operation is defined as RST = HI. 12 Min Typ - - - - 0.5465*Fso - 125 - SRC Mode - (Note 3) Bypass Mode - - Symbol Min 5.0 V CS8421 Max Units 0.4535*Fso Hz ±0.007 3/Fsi s Typ Max Units A 50 A 100 A 200 A 100 1 2 ...

Page 13

... SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge DS641F5 Symbol Symbol =- =- =- pF) L (Note 6) Crystal Digital Clock Source (Note 8) CS8421 Min Typ Max Units - - ± 250 - mV Min Max Units 0.77xVL - - .6 0.77xVL - - .6 0.77xVL - - .65 0.6xVL VL+0.3 -0.3 0.8 Symbol Min Max 1 - 16.384 27.000 1.024 27.000 14 ...

Page 14

... SDOUT (output) Figure 1. Non-TDM Slave Mode Timing 6. After powering up the CS8421, RST should be held low until the power supplies and clocks are settled. 7. The maximum possible sample rate is XTI/128. 8. OLRCK must remain high for at least 8 OSCLK periods in TDM Mode. 9. Only the input or the output serial port can be set as master at a given time. ...

Page 15

... The connection (VL or GND) and value of these two resistors determines the mode of operation for the input and output serial ports as described in DS641F5 +2 ILRCK ISCLK SDIN TDM_IN CS8421 MS_SEL SAIF SAOF SRC_UNLOCK BYPASS RST GND GND Table 2 on page 19 and Table 3 on page CS8421 +3 +5.0 V 0.1 F OLRCK Serial Audio OSCLK Input Device SDOUT XTI 19. 15 ...

Page 16

... SDOUT TDM_IN CS8421 MS_SEL SAIF XTI SAOF XTO SRC_UNLOCK BYPASS MCLK_OUT RST GND GND Table 1 Serial Audio Port Master/Slave and Clock Ratio Select Start-Up 19. CS8421 0.1 F Serial Audio Input Device Crystal /Clock Source To external ** 47 k hardware and Table 3, DS641F5 ...

Page 17

... The CS8421 does not require a control port interface, helping to speed design time by not requiring the user to de- velop software to configure the part. Pins that are sensed after reset allow the part to be configured. See Power-Down, and Start-Up” ...

Page 18

... Mode Selection The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes of operation. After reset, the resistor value and condition (VL or GND) are sensed. This operation will take approximately 4  complete. The SRC_UNLOCK pin will remain high and the SDOUT pin will be muted until the mode detection se- quence has completed ...

Page 19

... Left-Justified 16-bit data Left-Justified 20-bit data Left-Justified 24-bit data Left-Justified 32-bit data Right-Justified 16-bit data Right-Justified 20-bit data Right-Justified 24-bit data Right-Justified 32-bit data TDM Mode 16-bit data TDM Mode 20-bit data TDM Mode 24-bit data TDM Mode 32-bit data CS8421 ) ) x Fso) x Fso) 19 ...

Page 20

... When using the serial audio input port in Left-Justified and I²S Modes, all input data is treated as 32-bits wide. Any truncation that has been done prior to the CS8421 to less than 32-bits should have been done using an appropriate dithering process. If the serial audio input port is in Right-Justified Mode, the input data will be truncated to the bit depth set by SAIF pin setting ...

Page 21

... LRCK. In this case, MCLK will be synchronous to the master serial audio port. If both serial audio ports are set as slave, MCLK can be asynchronous to either or both ports. If the user needs to change the clock source to XTI while the CS8421 is still powered on and running, a RESET must be issued once the XTI clock source is present and valid to ensure proper operation. ...

Page 22

... CS8421’s output ports set to slave, as shown in The TDM_IN pin is used to input the data, while the SDOUT pin is used to output the data. The first CS8421 in the chain should have its TDM_IN set to GND. Data is transmitted from SDOUT most significant bit first on the first OSCLK falling edge after an OLRCK transition and is valid on the rising edge of OSCLK ...

Page 23

... Reset, Power-Down, and Start-Up When RST is low, the CS8421 enters a low-power mode, all internal states are reset, and the outputs are disabled. After RST transitions from low to high, the part senses the resistor value on the configuration pins (MS_SEL, SAIF, and SAOF) and sets the appropriate mode of operation. After the mode has been set (ap- proximately 4  ...

Page 24

... Power Supply, Grounding, and PCB Layout The CS8421 operates from +2.5 V and +5.0 V supply. These supplies may be set independently. Follow normal supply decoupling practices; see Extensive use of power and ground planes, ground-plane fill in unused areas, and surface-mount decou- pling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as the CS8421 to minimize inductance effects, and all decoupling capacitors should be as close to the CS8421 as possible ...

Page 25

... Figure 18. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz +0 -20 -40 -60 - -100 F S -120 -140 -160 -180 -200 30k 40k Figure 20. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz CS8421 20k 40k 60k 80k Hz Tone, 44.1 kHz:192 kHz 2.5k 5k 7.5k 10k 12.5k 15k 17.5k Hz Tone, 48 kHz:44.1 kHz 5k 10k 15k ...

Page 26

... Figure 24. Wideband FFT Plot (16k Points) -60 dBFS -60 -80 -100 d -120 -140 -160 -180 -200 15k 20k Figure 26. Wideband FFT Plot (16k Points) -60 dBFS CS8421 10k 20k 30k 40k Hz 1 kHz Tone, 48 kHz:96 kHz 20k 40k 60k 80k Hz 1 kHz Tone, 44.1 kHz:192 kHz 2.5k 5k 7.5k 10k 12 ...

Page 27

... Figure 30. IMD, 10 kHz and 11 kHz -7 dBFS, +0 -20 -40 -60 - -100 F S -120 -140 -160 -180 -200 15k 20k Figure 32. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz CS8421 5k 10k 15k 20k Hz 96 kHz:48 kHz 2.5k 5k 7.5k 10k 12.5k 15k 17. kHz:44.1 kHz 5k 10k 15k ...

Page 28

... B -135 F S -137.5 -140 -142.5 -145 -147.5 -150 15k 17.5k 20k Figure 38. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz CS8421 10k 20k 30k 40k Hz Tone, 48 kHz:96 kHz 5k 10k 15k 20k Hz Tone, 96 kHz:48 kHz 50k 75k 100k 125k 150k 175k ...

Page 29

... B -135 F S -137.5 -140 -142.5 -145 -147.5 -150 50k 150k 175k Figure 44. Dynamic Range vs. Output Sample Rate dBFS 1 kHz Tone, Fsi = 32 kHz CS8421 75k 100k 125k 150k 175k Hz Tone, Fsi = 96 kHz 75k 100k 125k 150k 175k Hz 75k 100k 125k 150k ...

Page 30

... Figure 48. Passband Ripple, 192 kHz:48 kHz +0 -10 -20 -30 -40 -50 d - -80 -90 -100 -110 -120 -130 -140 -140 -120 150k 175k Figure 50. Linearity Error -140 dBFS Input, 200 Hz CS8421 75k 100k 125k 150k 175k Hz 5k 10k 15k 20k 25k Hz -100 -80 -60 -40 -20 +0 dBFS Tone, 48 kHz:48 kHz DS641F5 ...

Page 31

... B - -80 -90 -100 -110 -120 -130 -140 -140 -120 -40 -20 +0 Figure 56. Linearity Error -140 dBFS Input, 200 Hz CS8421 -100 -80 -60 -40 -20 +0 dBFS Tone, 48 kHz:96 kHz -100 -80 -60 -40 -20 +0 dBFS Tone, 44.1 kHz:192 kHz -100 -80 -60 -40 -20 +0 dBFS Tone, 192 kHz:44.1 kHz ...

Page 32

... B -145 F S -150 -155 -160 -165 -170 -175 -180 -140 -120 -40 -20 +0 Figure 62. THD+N vs. Input Amplitude, 1 kHz Tone, CS8421 -100 -80 -60 -40 -20 +0 dBFS 48 kHz:96 kHz -100 -80 -60 -40 -20 +0 dBFS 44.1 kHz:192 kHz -100 -80 -60 -40 -20 +0 ...

Page 33

... B -145 F S -150 -155 -160 -165 -170 -175 -180 12.5k 15k 17.5k 20k 0 Figure 66. THD+N vs. Frequency Input, 0 dBFS, CS8421 -120 -100 -80 -60 -40 -20 dBFS 48 kHz:96 kHz 2.5k 5k 7.5k 10k 12.5k 15k 17. kHz:48 kHz +0 20k 33 ...

Page 34

... JEDEC #: MO-153 Controlling Dimension is Millimeters. Symbol 2 Layer Board 4 Layer Board CS8421 1 E1 END VIEW L MILLIMETERS NOM MAX -- 1.10 -- 0.15 0.90 0.95 0.245 0.30 6.50 6.60 6.40 6.50 4.40 4 ...

Page 35

... MIN -- 0.0394 -- -- 0.0020 0.00 0.0130 0.23 0.1240 3.05 0.1241 3.05 0.0276 0.50 JEDEC #: MO-220 Controlling Dimension is Millimeters. Symbol 2 Layer Board  Layer Board CS8421 Bottom View MILLIMETERS NOM MAX -- 1.00 -- 0.05 0.28 0.33 5.00 BSC 3.10 3.15 5.00 BSC 3.10 3.15 ...

Page 36

... Filter Characteristics” on page “ “Specified Operating Conditions” on page “Ordering Information” on page www.cirrus.com. CS8421 Container Order# Rail CS8421-CZZ Tape and Reel CS8421-CZZR Rail CS8421-CNZ Tape and Reel CS8421-CNZR Rail CS8421-DZZ Tape and Reel CS8421-DZZR Rail CS8421-EZZ Tape and Reel ...

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