AD9789 Analog Devices, AD9789 Datasheet
AD9789
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AD9789 Summary of contents
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... It can accept real or complex data. The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1 supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics ...
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... Digital Interface Modes ............................................................. 45 Analog Modes of Operation ..................................................... 54 Analog Control Registers .......................................................... 55 Voltage Reference ....................................................................... 56 DAC Output Stages .................................................................... 56 Clocking the AD9789 ................................................................ 57 Mu Delay Controller.................................................................. 58 Interrupt Requests...................................................................... 61 Recommended Start-Up Sequence .......................................... 62 Customer BIST Modes................................................................... 63 Using the Internal PRN Generator to Test QAM Output AC Performance................................................................................ 63 ...
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... BITS PATH 2 DATA BITS PATH 3 Figure 2. Digital Signal Processing Functional Block Diagram SRRC BYPASS QAM BYPASS SRRC Rev Page AD9789 BPF 16× INTERPOLATOR DAC SUM SCALE BPF f C 24-BIT NCO /16 DAC ...
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... AD9789 SPECIFICATIONS DC SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1 Table 1. Parameter DAC RESOLUTION ANALOG OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current (Monotonicity Guaranteed) Output Compliance Range Output Resistance Output Capacitance TEMPERATURE DRIFT Gain Reference Voltage REFERENCE Internal Reference Voltage ...
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... DAC FS Typ Max 3.3 0 0.8 +10 +10 2 3.3 0 0.85 1575 +100 25 120 1375 200 250 1250 140 0.37 1.8 900 2400 25 10 AD9789 Unit V V μA μ MHz Ω MSPS Ω MHz ...
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... AD9789 Parameter Minimum SCLK to SDIO Hold Maximum SCLK to Valid SDIO and SDO, t Minimum SCLK to Invalid SDIO and SDO, t INPUTS (SDIO, SCLK, CS) Input Voltage High Input Voltage Low Input Current High Input Current Low OUTPUTS (SDO, SDIO) ...
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... Four Carrier First Adjacent Channel Second Alternate Channel Third Alternate Channel 1 Adjusted DAC update rate is calculated as f divided by the minimum required interpolation factor. For the AD9789, the minimum interpolation factor is 16. Thus, DAC with f = 2400 MSPS 2400 MSPS/16 = 150 MSPS. DAC ...
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... AD9789 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating AVDD33 to AVSS −0 +3.6 V DVDD18 to DVSS −0 +1.98 V DVDD33 to DVSS −0 +3.6 V DVDD15 to DVSS −0 +1.98 V CVDD18 to AVSS −0 +1.98 V AVSS to DVSS −0 +0.3 V CLKP, CLKN to AVSS −0 CVDD18 + 0.3 V FS, DCO to DVSS −0 DVDD33 + 0.3 V CMOS and LVDS Data Inputs − ...
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... P+ M P– +LVDS 14 –LVDS Figure 7. LVDS Mode Data Input Pins (Top View) AD9789 DVDD15 FSP FSN 1 FS DCOP 1 FS DCON 0 DC ...
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... AD9789 Table 6. Pin Function Descriptions Pin No. Mnemonic A1, A2, A3, A6, A9, A10, A11, AVSS B1, B2, B3, B6, B7, B8, B9, B10, B11, C2, C3, C6, C7, C8, C9, C10, C11, D2, D3, D6, D7, D8, D9, D10, D11, E1, E2, E3, E4, E13, E14, F1, F2, F3, F4, F11, F12, F13, F14 A4, A5, B4, B5, C4, C5, D4, D5 ...
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... Active High Input. Enables CMOS_DCO and CMOS_FS signals and disables DCOP/DCON and FSP/FSN signals. Low input disables CMOS_DCO and CMOS_FS signals and enables DCOP/DCON and FSP/FSN signals. Serial Data Output for SPI. Active High Input. Resets the AD9789. CMOS/LVDS Data Input. CMOS/LVDS Data Input. CMOS/LVDS Data Input. ...
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... AD9789 TYPICAL PERFORMANCE CHARACTERISTICS –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 0 200 400 600 f (MHz) OUT Figure 8. SFDR vs. f over f , Full-Scale Current = 20 mA, OUT DAC Digital Scale = 0 dBFS, Temperature = 25°C –40 –45 –50 –55 –60 –65 –70 – ...
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... OUT over Temperature, 1-Channel QAM, f OUT Full-Scale Current = 20 mA AD9789 0dBFS –3dBFS –6dBFS –12dBFS 900 1000 1100 = 2.4 GHz, DAC +85°C +25°C –40°C 900 1000 1100 = 2.4 GHz, DAC +85°C +25°C –40°C ...
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... AD9789 –5 –15 –25 –35 –45 –55 –65 –75 –85 50 250 450 650 FREQUENCY (MHz) Figure 20. ACLR Performance over Temperature, 1-Channel QAM 2.3 GHz, Full-Scale Current = 20 mA, f DAC OUT (DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc) –55 –60 –65 –70 –75 – ...
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... OUT over Temperature (ACLR Measured Beyond 30 MHz), OUT = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32 DAC (DOCSIS SPEC Is −70 dBc) AD9789 DOCSIS3 25°C 65°C 85°C 1050 DOCSIS3 25°C 65°C 85°C 800 900 1000 DOCSIS3 25°C 65° ...
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... AD9789 0 –10 –20 –30 –40 –50 –60 –70 –80 50 250 450 650 FREQUENCY (MHz) Figure 32. ACLR Performance over Temperature, 4-Channel QAM 200 MHz 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20 OUT DAC (DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc) –55 –60 – ...
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... MHz, Sum Scale = 32, OUT Full-Scale Current = 25 mA, Span = 42 MHz, Channel 2 AD9789 UPPER dBc dBm UPPER dBc dBm ...
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... AD9789 REF –35.91dBm ATTEN 2dB CENTER 840.00MHz RES BW 30kHz VBW 300kHz SWEEP 58.4ms (601 PTS) FREQ. RMS RESULTS OFFSET REF BW dBc CARRIER POWER 3.375MHz 750.0kHz –75.37 –96.93 –21.56dBm/ 6.375MHz 5.250MHz –73.85 –95.41 6.00000MHz Figure 42. Zoomed 2-Channel QAM ACLR, f OUT Full-Scale Current = 25 mA, Span = 18 MHz, Channel 1 REF – ...
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... OUT f = 2.29376 GHz, Full-Scale Current = 25 mA, Sum Scale = 20 DAC AD9789 SPAN 18MHz UPPER dBc dBm –74.44 –97.64 –69.07 –92.26 +25°C +85°C –40°C 850 950 +25°C +85°C –40°C 850 950 ...
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... AD9789 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 f (MHz) OUT Figure 52. SFDR vs Mix Mode 2.4 GHz, Full-Scale Current = 20 mA OUT DAC (Second Nyquist Zone Performance ...
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... DAC , 4-Channel DOCSIS, f DAC SRRC Filter On, Four 2× Interpolation Filters On) TOTAL (CMOS) TOTAL (LVDS) 800 600 400 200 0 1.0 1.2 1.4 1.6 1.8 2.0 f (GHz) DAC Figure 61. Total Power Dissipation vs 16× Interpolation, DAC = 70 MHz, Full-Scale Current = 20 mA OUT AD9789 2.2 2.4 = 915 MHz, OUT 2.2 2.4 ...
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... AD9789 TERMINOLOGY Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of 0. For IOUTP output is expected when all inputs are set to 0. For IOUTN output is expected when all inputs are set to 1 ...
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... N1 PORT SDIO P1 Figure 62. Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT A write or read operation to the AD9789 is initiated by pulling CS low. CS stall high is supported in modes where three or fewer bytes of data (plus the instruction data) are transferred (see Table these modes, CS can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte ...
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... The default mode of the AD9789 serial control port is the uni- directional mode. In unidirectional mode, the readback data appears on the SDO pin also possible to set the AD9789 to bidirectional mode using the SDIO_DIR bit (Register 0x00[7]). In bidirectional mode, both the sent data and the readback data appear on the SDIO pin ...
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... Rev Page REGISTER (N – 1) DATA REGISTER (N – 3) DATA t C DON'T CARE DON'T CARE REGISTER ( DATA AD9789 LSB DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE ...
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... AD9789 SCLK SDIO Table 10. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between CS falling edge and SCLK rising edge (start of communication cycle) ...
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... SATERR Reserved LOCKACQ LOCKLOST SATERR Reserved CHANEN[3:0] INT[4:0] Reserved MAPPING[2:0] Reserved VER[3:0] IF_MODE CHANPRI PAR[1:0] CMPLX LTNCY[2:0] ONES[3:0] SNCPHZ[3:0] Reserved SPEC_INV AD9789 De- fault 0x18 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x0D 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ...
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... AD9789 Addr Register Name Bit 7 0x2F Mu Delay SEARCH_ Control 1 TOL 0x30 Mu control duty Duty cycle cycle correct enable 0x31 Clock Receiver 1 0x32 Clock Receiver 2 CLK_DIS 0x33 Mu Delay MU_CLKDIS Control 2 0x34 Reserved 0x35 Reserved 0x36 DAC bias PDBIAS 0x37 Reserved 0x38 DAC decoder ...
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... Interrupt Bit 2 being set in Register 0x04 and the IRQ pin going low. 1 SATERR Setting this bit to 1 enables a SATERR (overflow into 16× interpolator) flag to generate an interrupt request. Generating an interrupt request results in Interrupt Bit 1 being set in Register 0x04 and the IRQ pin going low. 0 Reserved Reserved. Rev Page AD9789 ...
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... AD9789 Table 16. Interrupt Status/Clear Register (Address 0x04) Bit Name Description 7 PARERR If this bit is set to 1, one or more parity errors has occurred. Writing this bit clears the interrupt. 6 BISTDONE If this bit is set to 1, the BIST has reached the terminal state. Writing this bit clears the interrupt. ...
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... Alpha Filter 0.12 0.18 0.15 0.13 QAM Encoding DOCSIS 64-QAM DOCSIS 256-QAM DVB-C 16-QAM DVB-C 32-QAM DVB-C 64-QAM DVB-C 128-QAM DVB-C 256-QAM Unused 2.6 Multiplier 0 0.015625 0.03125 … 0.203125 (default) … 3.96875 3.984375 3.5 Multiplier 0 0.03125 0.0625 … 1 (default) … 7.9375 7.96875 Rev Page AD9789 ...
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... AD9789 The three NCO 0 frequency tuning word registers together compose the 24-bit frequency tuning word for NCO 0. For more information about programming these registers, see the Baseband Digital Upconverter section. Table 22. NCO 0 Frequency Tuning Word Registers (Address 0x0A to Address 0x0C) Address ...
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... Bit Name Description 7 FREQNEW Setting this bit to 1 updates the derived registers in the AD9789. This bit must be set for changes to Register 0x16 through Register 0x1D to take effect. This self-clearing bit is reset to 0 after the derived registers are updated. [6:0] Reserved Reserved. Table 30. Hardware Version Register (Address 0x1F) ...
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... AD9789 Table 32. Data Control Register (Address 0x21) Bit Bit Name Description 7 BIN This bit selects the coding for the device twos complement coding straight binary coding. [6:5] BUSWDTH[1:0] These bits set the input data bus width for the device. Setting ...
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... These registers configure a value for the 1.7 multiplier applied to each individual channel just prior to the SUMSCALE block. The range of the channel gain 1.9921875 with a step size of 0.0078125. To mute an individual channel, set the scale factor to 0. Setting 00000000 00000001 … 11111111 Rev Page AD9789 Channel Gain 0 0.0078125 … 1.9921875 ...
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... Bit Bit Name Description 7 CLK_DIS This bit disables or enables the clock receiver. When the AD9789 powers up, this bit is set prevent severe output noise that occurs on power-up with no clock. When the DAC clock is stable, set this bit disabled enabled. 6 Reserved Reserved (factory use only ...
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... Table 44. DAC Decoder Register (Address 0x38) Bit Bit Name Description [7:2] Reserved Reserved. [1:0] DAC decoder These bits set the decoder mode for the DAC recommended that normal mode (the default) be used. mode 00 = normal mode return to zero mode mix mode invalid. Rev Page AD9789 ...
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... AD9789 Table 45. Mu Delay Control 3 Register (Address 0x39) Bit Bit Name Description 7 MUDLY[0] This bit is the LSB of the mu delay value. Along with Bits[7:0] in Register 0x3A, this bit configures the programmable mu delay; the search algorithm begins at this specified mu delay value. In manual mode, the MUDLY bits can be written to ...
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... NCO Figure 70. Top Level Functional Block Diagram DATAPATH SIGNAL PROCESSING The DSP blocks included on the AD9789 can be grouped into two sections. The first is the datapath signal processing. Four identical datapaths, or channels, can be used. A block diagram of a single channel is shown in Figure 71. Enabling and disabling each DSP block within the datapath takes effect on all channels ...
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... AD9789 Table 50. QAM Mapper Input and Output Range vs. Mode ITU-T J.83 Annex Description B DOCSIS 64-QAM B DOCSIS 256-QAM A DVB-C 16-QAM A DVB-C 32-QAM A and C DVB-C 64-QAM A and C DVB-C 128-QAM A and C DVB-C 256-QAM Unused don’t care. Each constellation point corresponds and Q coordinate pair, as shown in Figure 74 ...
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... Half-Band Interpolation Filters The AD9789 can provide from 1× to 32× interpolation through the datapath using five bypassable half-band interpolation filters. The half-band interpolation filters are controlled via Register 0x06[4:0]. The preferred order in terms of power savings for bypassing these filters is to bypass Filter 0 first, then Filter 1, and so on ...
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... AD9789 Sample Rate Converter The purpose of the sample rate converter (SRC provide increased flexibility in the ratio of the input baud rate to the DAC update rate. Each of the four channelization datapaths contains a sample rate converter (SRC) that provides a data rate conversion in the range of 0.5 to 1.0 inclusive. The rate conversion factor is set by the ratio of two 24-bit values, P and Q ...
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... CHANxGAIN[7:0] Figure 85. Individual Channel Gain Control DIGITAL BLOCK UPCONVERTER The second half of the DSP engine on the AD9789 combines the outputs of the four datapaths into one block, scales the block of channels, interpolates by 16× to the full DAC rate, and performs Channel 2 Channel 3 a band-pass filter operation allowing the block of channels to be Reg ...
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... AD9789 Table 54 shows recommended sum scale values for each QAM mapper mode. The criteria used to determine the recommended sum scale values were MER/EVM measurements and spectral purity. Because clipping results in impulsive noise, it can be observed in the output spectrum as a transient increase in the output noise floor ...
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... The bus width, which is the physical width of the digital data bus at the input of the AD9789, can be set to a 4-, 8-, 16-, or 32-bit wide interface. The data width, which is the internal width of the data at the input to the digital datapath, can be set to an 8-bit or 16-bit word ...
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... AD9789 In LVDS mode, the various interface width options are mapped to the AD9789 input pins as shown in Table 57. When the inter- face width is set to 32 bits in LVDS mode, the interface becomes double data rate (DDR). In DDR mode, the first 16 bits are sampled on the rising edge of the data sampling clock (DSC, which is synchronous to DCO), and the second 16 bits are sampled on the falling edge of DSC ...
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... Channel 3 Channel 2 Channel 1 Channel 3 Channel 1 CMOS I AND BITS LVDS RISE I AND Q OFF 16 BITS I AND Q CMOS OFF Q 16 BITS LVDS FALL I AND Q OFF 16 BITS Figure 93. QDUC Mode AD9789 [D7:D0] Channel 0 Channel 1 Channel 1 [D7:D0] Channel 0 BPF DAC BPF f C ...
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... P D[31:0] CMOS DATA INPUTS PARITY AND CONTROL INPUTS Figure 94. CMOS Data Input Pin Mapping In LVDS mode, the AD9789 input pins are mapped as shown in Table 65. Table 65. Pin Mapping in QDUC Mode for LVDS Interface Data Bit Description D15P, D15N rising MSB of I data ...
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... PD between the rising edge of FS and when the first sample in a given transmission is sampled into the AD9789. Note that t can vary by more than 1 DCO cycle. Retimer Operation The AD9789 uses a three-register retimer. The first two registers are clocked from any one of 16 phases derived from the DAC clock ...
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... GHz. To use Table 66 and Table 67, probe the FS, DCO, and data input signals at the AD9789. While viewing these signals on an oscilloscope, measure the delay between the rising edge of FS and the start of the first data sample and add 1.6 ns from the delay of the pins to this value ...
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... LAT SNC DSC Delay LAT SNC 7 DSC 0 Rev Page AD9789 100 101 102 105 106 107 108 109 110 7 ...
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... INTERFACE these available DCO cycles between FS. This decrease in available DCO cycles is a result of the round-trip propagation delay from the FS output of the AD9789 to the respective data sample at the input of the AD9789 (LTNCY[2:0]) in addition to the internal latency of the device. For a successful interface design, the following condition must ...
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... DCO Odd Parity If parity checking is used, each data-word that is transferred into the AD9789 should have a parity bit accompanying it, regardless of FS. In other words, parity must be valid for every DCO edge. The parity bits are located at Pin L4 and Pin M4. When operating the interface in CMOS mode, the input parity bits are referred and P0, respectively ...
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... PARN falling = 0 be cleared by writing Register 0x04[7]. ANALOG MODES OF OPERATION The AD9789 uses a quad-switch architecture that can be config- ured to operate in one of three modes via the serial peripheral interface: normal mode, RZ mode, and mix mode. The quad-switch architecture masks the code-dependent glitches that occur in a conventional two-switch DAC ...
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... The RZ mode, with its lower but flat response, can be quite useful for quick checks of system frequency response D10 ANALOG CONTROL REGISTERS The AD9789 includes registers for optimizing its analog performance. These registers include noise reduction in the –D8 –D7 –D9 output current mirror and output current mirror headroom –D10 adjustments ...
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... Figure 109. Full-Scale Current vs. DAC Gain Code Always connect a 10 kΩ resistor from the I120 pin to ground and use the digital controls to adjust the full-scale current. The AD9789 is not a multiplying DAC. Applying an analog signal to I120 is not supported. VREF (Pin C14) must be bypassed to ground with capacitor ...
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... Figure 111 to avoid unnecessary parasitics. CLOCKING THE AD9789 To provide the required signal swing for the internal clock receiver of the AD9789 necessary to use an external clock buffer chip to drive the CLKP and CLKN inputs. These high level, high slew rate signals should not be routed any distance on a PCB ...
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... PSIGN/NSIGN Clock Phase Noise Effects on AC Performance The quality of the clock source driving the ADCLK914 deter- mines the achievable ACLR performance of the AD9789. Table 76 summarizes the close-in ACLR for a four-carrier DOCSIS signal at 900 MHz with respect to various phase noise profiles. (All ACLR values are specified in dBc.) Table 76 ...
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... Examples of valid and invalid phase choices are shown in Figure 119 and Figure 120 DESIRED 11 10 POSITIVE SLOPE Figure 119. Valid Positive and Negative Slope Phase Examples Rev Page AD9789 DESIRED PHASE AND GUARD SLOPE BAND 200 240 280 320 360 ...
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... The program assumes that the clock receiver is already enabled 3 and that a clean lock is provided. The typical locking time for 2 the mu controller is approximately 180,000 DAC cycles (at DESIRED 2 GSPS, ~75 μs Table 78. AD9789 Mu Delay Controller Routine Address 0x30 0x31 0x32 0x3E 0x24 0x24 0x2F ...
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... If the pin is used to determine that an interrupt has occurred necessary to check Register 0x04 to determine which bit caused the interrupt because the pin indicates only that an interrupt has occurred. To clear an IRQ necessary to write the bit in Register 0x04 that corresponds to the interrupt. Rev Page AD9789 ...
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... RECOMMENDED START-UP SEQUENCE The steps necessary to optimize the performance of the part and generate an output waveform are listed in Table 79. Table 79. Recommended System Start-Up Sequence Step Description 0 Power up the AD9789. 0 Apply the clock. 1 Enable the clock receiver and set the clock CML. 1 Enable duty cycle correction. ...
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... CUSTOMER BIST MODES USING THE INTERNAL PRN GENERATOR TO TEST QAM OUTPUT AC PERFORMANCE The AD9789 can be configured to enable an on-chip pseudo- random number (PRN) generator. The PRN output is connected to the front end of the datapath and disconnects the datapath from the input pins. In this way, the PRN generator can be used in conjunction with the on-chip QAM encoder to generate a QAM output ...
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... AD9789 4. Configure pin mode by setting the registers in Table 85 to the values shown in the table. Table 85. Register Settings to Configure Pin Modes Register Setting 0x42 0x00 0x43 0x08 0x44 0x00 0x45 0x08 0x46 0x00 0x47 0x10 0x49 0x1C 0x4B 0x1C 0x4C 0x00 0x4D 0x00 5 ...
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... π ROTATION I Q ARE THE TWO MSBs IN EACH QUADRANT Figure 124. DVB -C128-QAM Constellation3 AD9789 11100 11101 11110 11111 01110 01111 01100 01101 ...
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... AD9789 π 110,111 111,011 010,111 011,011 100,101 101,111 110,101 111,111 110,100 111,000 010,100 011,000 100,000 101,010 110,000 111,010 100,111 101,011 000,111 001,011 000,101 001,111 010,101 011,111 100,100 101,000 000,100 001,000 000,000 001,010 010,000 011,010 010,011 011,001 000,011 001,001 000,001 001,101 100,001 101,101 ...
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... AD9789 ...
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... AD9789 CHANNELIZER MODE PIN MAPPING FOR CMOS AND LVDS Table 93 lists the available combinations of data input configu- ration parameters when the AD9789 is in channelizer mode. Many of these configurations require multiple clocks to load all channels. All of these configurations are described in detail in Table 96 and Table 97. ...
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... CMOS Pin Mapping [D27:D24] [D23:D20] [D19:D16] CMOS Pin Mapping [D27:D24] [D23:D20] [D19:D16] CMOS Pin Mapping [D27:D24] [D23:D20] [D19:D16] CMOS Pin Mapping [D27:D24] [D23:D20] [D19:D16] Rev Page AD9789 [D15:D12] [D11:D8] [D7:D4] [D3:D0 [D15:D12] [D11:D8] [D7:D4] [D3:D0 ...
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... AD9789 Datapath Configuration BW DW Format DCO [D31:D28 Complex Datapath Configuration BW DW Format DCO [D31:D28 Real 1 2 Datapath Configuration BW DW Format DCO [D31:D28 Complex Datapath Configuration BW DW Format DCO ...
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... LVDS Pin Mapping DCO [D15:D12] [D11:D8 LVDS Pin Mapping DCO [D15:D12] [D11:D8 Rev Page AD9789 [D7:D4] [D3:D0 [D7:D4] [D3:D0 [D7:D4] [D3:D0 ...
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... AD9789 Datapath Configuration BW DW Format 8 16 Complex Datapath Configuration BW DW Format 16 8 Real Datapath Configuration BW DW Format 16 8 Complex Datapath Configuration BW DW Format 16 16 Complex Datapath Configuration BW DW Format 32 8 Real Datapath Configuration BW DW Format 32 8 Complex LVDS Pin Mapping DCO ...
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... Datapath Configuration BW DW Format 32 16 Complex LVDS Pin Mapping DCO [D15:D12] [D11:D8] 1 rise 1 fall 2 rise 2 fall 3 rise 3 fall 4 rise 4 fall Rev Page AD9789 [D7:D4] [D3:D0 ...
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... CORNER * 1.30 1.22 1.14 ORDERING GUIDE Model 1 Temperature Range AD9789BBCZ −40°C to +85°C AD9789BBCZRL −40°C to +85°C AD9789BBC −40°C to +85°C AD9789BBCRL −40°C to +85°C AD9789-EBZ AD9789-MIX-EBZ RoHS Compliant Part. 12.00 BSC SQ 14 10.40 BSC SQ 0.80 BSC 0.80 TOP VIEW REF DETAIL A 0.65 REF ...
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... NOTES Rev Page AD9789 ...
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... AD9789 NOTES ©2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07852-0-7/11(A) Rev Page ...