AD9788 Analog Devices, AD9788 Datasheet
AD9788
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AD9788 Summary of contents
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... Dual 12-/14-/16-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO GENERAL DESCRIPTION The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit, high dynamic range TxDAC® devices, respectively, that provide a sample rate of 800 MSPS, permitting multicarrier generation up to the Nyquist frequency. Features are included for optimizing ...
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... Driving the REFCLK Input ........................................................... 47 DAC REFCLK Configuration ................................................... 47 Analog Outputs............................................................................... 50 Digital Amplitude Scaling ......................................................... 50 Power Dissipation ........................................................................... 52 AD9785/AD9787/AD9788 Evaluation Boards........................... 54 Output Configuration ................................................................ 54 Digital Picture of Evaluation Board ......................................... 54 Evaluation Board Software ........................................................ 55 Evaluation Board Schematics ................................................... 56 Outline Dimensions ....................................................................... 62 ...
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... Rev Page AD9785/AD9787/AD9788 = 20 mA, maximum sample rate, unless OUTFS AD9787 AD9788 Typ Max Min Typ 14 16 ±0.5 ±2.1 ±1.0 ±3.7 0 +0.001 −0.001 0 ±2 ±2 20.2 31.66 8.66 20.2 +1.0 –1 0.04 0.04 100 100 30 30 ...
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... AD9785/AD9787/AD9788 DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input V Logic High IN Input V Logic Low IN LVDS INPUT (SYNC_I+, SYNC_I−) Input Voltage Range Input Differential Threshold, V IDTH Input Differential Hysteresis, V − ...
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... Rev Page AD9785/AD9787/AD9788 Min Typ Max 40 83 155 294 18 260 mA, maximum sample rate, unless AD9787 AD9788 Typ Max Min Typ Max Unit 82 83 dBc 82 83 dBc 80 81 dBc 87 90 dBc 82 83 dBc 79 80 ...
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... AD9785/AD9787/AD9788 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating AVDD33 to AGND, DGND, CGND −0 +3.6 V DVDD33, DVDD18, CVDD18 −0 +2 AGND, DGND, CGND AGND to DGND, CGND −0 +0.3 V DGND to AGND, CGND −0 +0.3 V CGND to AGND, DGND −0 +0.3 V I120, VREF, IPTAT to AGND − ...
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... Port 1, Data Input D11 (MSB). Port 1, Data Input D10. Port 1, Data Input D9. Port 1, Data Input D8. Port 1, Data Input D7. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Port 1, Data Input D2. Rev Page AD9785/AD9787/AD9788 75 I120 VREF 74 IPTAT 73 AGND 72 71 IRQ ...
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... AD9785/AD9787/AD9788 Pin No. Mnemonic 29 P1D[1] 30 P1D[ DATACLK 38, 61 DVDD33 39 TXENABLE 40 P2D[11] 41 P2D[10] 42 P2D[9] 45 P2D[8] 46 P2D[7] 47 P2D[6] 48 P2D[5] 49 P2D[4] 50 P2D[3] 51 P2D[2] 52 P2D[1] 55 P2D[0] 62 SYNC_O− 63 SYNC_O+ 65 PLL_LOCK 66 SPI_SDO 67 SPI_SDIO 68 SCLK 69 SPI_CSB 70 RESET 71 IRQ 73 IPTAT 74 VREF 75 I120 76, 78, 80, 96, 98, 100 ...
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... Port 1, Data Input D11. Port 1, Data Input D10. Port 1, Data Input D9. Port 1, Data Input D8. Port 1, Data Input D7. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Port 1, Data Input D2. Rev Page AD9785/AD9787/AD9788 75 I120 VREF 74 IPTAT 73 72 AGND IRQ 71 ...
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... AD9785/AD9787/AD9788 Pin No. Mnemonic 31 P1D[1] 34 P1D[0] 35, 36, 58 DATACLK 38, 61 DVDD33 39 TXENABLE 40 P2D[13] 41 P2D[12] 42 P2D[11] 45 P2D[10] 46 P2D[9] 47 P2D[8] 48 P2D[7] 49 P2D[6] 50 P2D[5] 51 P2D[4] 52 P2D[3] 55 P2D[2] 56 P2D[1] 57 P2D[0] 62 SYNC_O− 63 SYNC_O+ 65 PLL_LOCK 66 SPI_SDO 67 SPI_SDIO 68 SCLK 69 SPI_CSB 70 RESET 71 IRQ 73 IPTAT 74 VREF 75 I120 76, 78, 80, 96, 98, 100 ...
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... P1D[12] 20 P1D[11] 21 DGND 22 DVDD18 23 P1D[10] 24 P1D[ Table 8. AD9788 Pin Function Descriptions Pin No. Mnemonic CVDD18 CGND 5 REFCLK+ 6 REFCLK− 12, 72, 77, 79, 81, 82, 85, AGND 88, 91, 94, 95, 97, 99 ...
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... AD9785/AD9787/AD9788 Pin No. Mnemonic 31 P1D[3] 34 P1D[2] 35 P1D[1] 36 P1D[0] 37 DATACLK 38, 61 DVDD33 39 TXENABLE 40 P2D[15] 41 P2D[14] 42 P2D[13] 45 P2D[12] 46 P2D[11] 47 P2D[10] 48 P2D[9] 49 P2D[8] 50 P2D[7] 51 P2D[6] 52 P2D[5] 55 P2D[4] 56 P2D[3] 57 P2D[2] 58 P2D[1] 59 P2D[0] 62 SYNC_O− 63 SYNC_O+ 65 PLL_LOCK 66 SPI_SDO 67 SPI_SDIO 68 SCLK 69 SPI_CSB 70 RESET 71 IRQ 73 IPTAT 74 VREF 75 I120 76, 78, 80, 96, 98, 100 ...
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... OUT Figure 7. AD9785 ACLR, 4× Interpolation, f 2× 80 100 , Multitone Input, OUT 4× 80 100 , Single-Tone Input, OUT 260 = 122.88 MSPS DATA Rev Page AD9785/AD9787/AD9788 100 95 200 MSPS 250 MSPS 90 85 160 MSPS ...
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... MSPS, DATA 280 320 360 400 Figure 15. AD9787 Noise Spectral Density vs. f 250MSPS 200MSPS 80 100 , 2× Interpolation Figure 16. AD9788 ACLR for First Adjacent Band WCDMA, 4× Interpolation, OUT Rev Page –142 –146 –150 –154 –158 1× –162 –166 –170 ...
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... PLL OFF 0 dBFS PLL OFF – 100 120 140 160 180 200 220 240 f (MHz) OUT Figure 18. AD9788 ACLR for Third Adjacent Band WCDMA, 4× Interpolation 122.88 MSPS, NCO Translates Baseband Signal to IF DATA 100 160MSPS 90 80 200MSPS 70 60 ...
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... Interpolation 200 MSPS DATA 100MSPS 300 350 400 450 –6dBFS –3dBFS 280 320 360 400 Figure 27. AD9788 Noise Spectral Density vs. Digital Full-Scale Single-Tone 280 320 360 400 Figure 28. AD9788 Noise Spectral Density vs. f Rev Page 100 ...
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... Single-Tone Input, OUT 2× 4× 80 100 , Eight-Tone Input Figure 33. AD9788 Out-of-Band SFDR vs. f DAC 1× 2× 4× 80 100 , Full-Scale Single-Tone Figure 34. AD9788 In-Band SFDR vs. Full-Scale Output Current, Rev Page AD9785/AD9787/AD9788 90 85 200MSPS 80 160MSPS ...
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... Figure 36. AD9788 Out-of-Band SFDR vs 0dBFS 85 80 –6dBFS (MHz) OUT Figure 37. AD9788 In-Band SFDR vs. Digital Full-Scale Input, 2× Interpolation 200 MSPS DATA 200MSPS 4× Interpolation OUT 200MSPS 4× Interpolation OUT –3dBFS Rev ...
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... OUT Figure 41. AD9788 In-Band SFDR vs 4× Interpolation, f OUT PLL On/PLL Off PLL OFF PLL 100 MSPS, DATA Rev Page AD9785/AD9787/AD9788 ...
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... AD9785/AD9787/AD9788 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. ...
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... One optional pin, SPI_CSB (chip select), allows enabling of multiple devices on a single bus. With the AD9785/AD9787/AD9788, the instruction byte specifies read/write operation and the register address. Serial operations on the AD9785/AD9787/AD9788 occur only at the register level, not at the byte level, due to the lack of byte address space in the instruction byte. + SIN(× ...
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... The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9785/AD9787/ AD9788. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9785/AD9787/AD9788 and the system controller ...
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... If the LSB mode is active, the serial port controller generates the least significant byte address first, followed by the next greater significant byte addresses until the I/O operation is complete. All data written to or read from the AD9785/AD9787/AD9788 must be in LSB first order. SPI Resynchronization Capability ...
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... AD9785/AD9787/AD9788 SPI REGISTER MAP When reading Table 9, note that the AD9785/AD9787/AD9788 is a 32-bit part and, therefore, the 4 with the MSB and ending with the LSB) represent a set of eight bits. Refer to the Bit Range column for the actual bits being described. Table 9. ...
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... Serial interface accepts serial data in LSB first format. 0: Default. Bit is in the inactive state the AD9785/AD9787/AD9788, all programmable bits return to their power-up state except for the COMM register bits, which are unaffected by the software reset. The software reset remains in effect until this bit is set to 0 (inactive state). ...
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... AD9785/AD9787/AD9788 The digital control (DCTL) register comprises two bytes located at Address 0x01. Table 11. Digital Control (DCTL) Register Address Bit Name 0x01 [15] Reserved [14] Clear phase accumulator [13] PN code sync enable [12] Sync mode select [11] Pulse sync enable [10] Reserved [9] Inverse sinc enable [8] DATACLK output enable ...
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... Default. The digital input data sampling edge is aligned with the falling edge of DCI. 1: The digital input data sampling edge is aligned with the rising edge of DCI. Used only in slave mode (see the MSCR register, Address 0x03, Bit 16). Reserved for future use. Rev Page AD9785/AD9787/AD9788 ...
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... SYNC_O is generated on the falling edge of DACCLK. 0: Default. The AD9785/AD9787/AD9788 are not operating in internal loopback mode the SYNC_O enable and Sync loopback enable bits are set, the AD9785/AD9787/AD9788 are operating in a mode in which the internal synchronization pulse of the device is used at the multichip receiver logic and the SYNC_I+ and SYNC_I− input pins are ignored. For proper operation of the loopback synchronization mode, the synchronization driver enable and sync enable bits must be set ...
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... Default. If the I DAC power-down bit is cleared, the I DAC is active the I DAC power-down bit is set, the I DAC is inactive and enters a low power state. Reserved for future use. These bits are the I DAC gain adjustment bits. Rev Page AD9785/AD9787/AD9788 /f . VCO DACCLK /f ...
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... AD9785/AD9787/AD9788 The Auxiliary DAC 1 control register comprises two bytes located at Address 0x06. These bits are routed directly to the periphery of the digital logic. No digital functionality within the main digital block is required. Table 16. Auxiliary DAC 1 Control Register Address Bit Name 0x06 [15] Auxiliary DAC 1 sign ...
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... The sync IRQ bit (and the IRQ pin) are enabled and go active if a setup or hold error is detected via the multichip synchronization receive pulse setup/hold error checking logic. Rev Page AD9785/AD9787/AD9788 ...
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... AD9785/AD9787/AD9788 The frequency tuning word (FTW) register comprises four bytes located at Address 0x0A. Table 20. Frequency Tuning Word (FTW) Register Address Bit Name 0x0A [31:0] Frequency Tuning Word [31:0] The phase control register (PCR) comprises four bytes located at Address 0x0B. Table 21. Phase Control Register (PCR) ...
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... INPUT DATA REFERENCED TO DATACLK The simplest method of interfacing to the AD9785/AD9787/ AD9788 is when the input data is referenced to the DATACLK output. The DATACLK output is phase-locked (with some offset) to the internal clock that is used to latch the input data. ...
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... AD9785/AD9787/AD9788 DATACLK INPUT DATA QFIRST = 0 QFIRST = 1 Table 25. Data Timing Specifications vs. Temperature Timing Parameter Temperature Data with respect to REFCLK −40°C +25°C +85°C −40°C to +85°C Data with respect to DATACLK −40°C +25°C +85°C −40°C to +85°C SYNC_I with respect to REFCLK − ...
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... Device Synchronization section. The timing relationships between SYNC_I, DACCLK, REFCLK, and the input data are shown in Figure 49 through Figure 51. t H_SYNC t S_SYNC t HREFCLK t SREFCLK Figure 49. REFCLK 2× t H_SYNC t S_SYNC t t SREFCLK HREFCLK Figure 50. REFCLK 4× Rev Page AD9785/AD9787/AD9788 ...
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... REFCLK INPUT DATA OPTIMIZING THE DATA INPUT TIMING The AD9785/AD9787/AD9788 have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the DATACLK output and DCLK_SMP, the internal clock that samples the input data. This optimization is made by a sequence of SPI register read and write operations ...
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... Any change to the Data Timing Margin [3:0] or DATACLK Delay [4:0] values triggers a new error check operation. INPUT DATA RAM The AD9785/AD9787/AD9788 feature on-chip RAM that can be used as an alternative input data source to the input data pins. The input data RAM is loaded through the SPI port. After the ...
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... A 32-bit NCO provides the sine and cosine carrier signals required for the quadrature modulator. INTERPOLATION FILTERS The AD9785/AD9787/AD9788 contain three half-band filters that can be bypassed. This allows the device to operate with 2×, 4×, or 8× interpolation rates, or without interpolation. The interpolation filters have a linear phase response ...
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... H(6) +72 H(7) 0 H(8) −138 H(9) 0 H(10) +245 H(11) 0 H(12) −408 Table 30. Half-Band Filter 3 0 Lower Coefficient +650 H(1) 0 H(2) −1003 H(3) 0 H(4) +1521 H(5) 0 H(6) −2315 H(7) 0 H(8) +3671 0 −6642 0 +20,755 +32,768 Rev Page AD9785/AD9787/AD9788 Upper Coefficient Integer Value H(23) −2 H(22) 0 H(21) +17 H(20) 0 H(19) −75 H(18) 0 H(17) +238 H(16) 0 H(15) −660 H(14) 0 H(13) +2530 +4096 Upper Coefficient Integer Value H(15) −39 H(14) 0 H(13) +273 H(12) 0 H(11) −1102 H(10) 0 H(9) +4964 ...
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... By default, when an SPI write is completed for the frequency tuning word, phase control, DAC gain scaling, or DAC offset registers (Register 0x0A through Register 0x0D), the operation of the AD9785/AD9787/AD9788 is immediately updated to reflect these changes. However, in many applications it may be more useful to update these registers without changing the device operation until all these functions can be updated at once ...
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... Q DAC output moves approximately 14° towards the I DAC output, creating an angle of 76° between the channels. Based on these two endpoints, the resolution of the phase compensation register is approximately 28°/1024 or 0.027° per code. and I OUTx_P OUTx_N Rev Page AD9785/AD9787/AD9788 0x0000 0x4000 ...
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... NCO phase accumulator of the device to a particular clock edge of the system clock. The AD9785/AD9787/AD9788 support two modes of operation, pulse mode and PN code mode, for synchronizing devices under these two conditions. ...
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... SYNC_I DELAY [4:0] SYNC_I ENABLE Figure 60. Synchronization Receive Circuitry Block Diagram SYSTEM CLOCK LOW SKEW CLOCK DRIVER PULSE GENERATOR LOW SKEW CLOCK DRIVER Figure 61. Multichip Synchronization in Pulse Mode AD9785/AD9787/AD9788 DACCLK CLOCK GENERATION STATE LD-STATE CLOCK STATE [3:0] PULSE MODE 0 1 ENABLE EDGE DETECTOR ...
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... AD9785/AD9787/AD9788 SYNCHRONIZING DEVICES TO A SYSTEM CLOCK The AD9785/AD9787/AD9788 offer a pulse mode synchron- ization scheme (see Figure 61) to align the DAC outputs of multiple devices within a system to the same DAC clock edge. The pulse mode synchronization scheme is a two-part operation. First, the internal clocks are synchronized by providing either a one-time pulse or periodic signal to the SYNC_I (SYNC_I+/SYNC_I− ...
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... OTHER 0 1 The AD9785/AD9787/AD9788 synchronization engine uses a PN code synchronization scheme to align multiple devices within a system to the same DAC clock edge. The PN code scheme synchronizes all the internal clocks, as well as the phase accumulator of the NCO for all devices. With this scheme, one device functions as the master, and the remainder of the devices are configured as slaves ...
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... AD9785/AD9787/AD9788 Table 33 lists the register settings required to enable the PN code mode synchronization feature. Table 33. Register Settings for Enabling PN Code Mode Register Bit Parameter 0x01 [13] PN code sync enable [12] Sync mode select [11] Pulse sync enable 0x03 [31:27] Correlate Threshold [4:0] [26] SYNC_I enable [25] SYNC_O enable ...
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... Figure 67. REFCLK V Generator Circuit CM DAC REFCLK CONFIGURATION The AD9785/AD9787/AD9788 offer two modes of sourcing the DAC sample clock (DACCLK). The first mode employs an on-chip clock multiplier that accepts a reference clock operating at the lower input frequency, most commonly the data input frequency. The on-chip phase-locked loop (PLL) then multiplies the reference clock higher frequency, which can then be used to generate all the internal clocks required by the DAC ...
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... AD9785/AD9787/AD9788 (PIN 5 AND PIN 6) Table 35. Typical VCO Freq Range vs. PLL Band Select Value PLL Lock Ranges over Temperature, −40°C to +85°C VCO Frequency Range in MHz PLL Band Select f LOW 111111 (63) Auto mode 111110 (62) 1975 111101 (61) 1956 111100 (60) 1938 111011 (59) ...
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... Read back the 6-bit PLL band select value (Register 0x04, Bits [7:2]). AD9785/AD9787/AD9788 4. Based on the temperature when the PLL auto mode is enabled, set the PLL band indicated in Table 36 or Table 37 by rewriting the readback values into the PLL Band Select [5:0] parameter (Register 0x04, Bits [7:2]) ...
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... Auxiliary DAC Operation Two auxiliary DACs are provided on the AD9785/AD9787/ AD9788. The full-scale output current on these DACs is derived from the 1.2 V band gap reference and external resistor. The gain scale from the reference amplifier current approximately FS auxiliary DAC reference current is 16 ...
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... PASSIVE I INPUTS FILTERING 0.1µF 0.1µF OPTIONAL Q DAC PASSIVE FILTERING 0.1µF 25Ω TO 50Ω AUX DAC1 OR DAC2 OPTIONAL DAC PASSIVE FILTERING 25Ω TO 50Ω 25Ω TO 50Ω Rev Page AD9785/AD9787/AD9788 QUADRATURE AUX DAC2 QUAD MOD Q INPUTS QUAD MOD I AND Q INPUTS ...
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... AD9785/AD9787/AD9788 POWER DISSIPATION Figure 74 through Figure 78 detail the power dissipation of the AD9785/AD9787/AD9788 under a variety of operating conditions. All of the graphs are taken with data being supplied to both the I and Q channels. The power consumption of the device does not vary significantly with changes in the modulation mode or analog output frequency ...
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... DAC Figure 78. Digital 1.8 V Supply, Power Dissipation of Inverse Sinc Filter 800 1000 Rev Page AD9785/AD9787/AD9788 ...
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... AD9785/AD9787/AD9788 AD9785/AD9787/AD9788 EVALUATION BOARDS The remainder of this data sheet describes the evaluation boards for testing the AD9785, AD9787, and AD9788 devices. OUTPUT CONFIGURATION Each evaluation board contains an Analog Devices ADL5372 quadrature modulator. The AD9785/AD9787/AD9788 devices and the ADL5372 provide an easy-to-interface DAC/modulator combination that can be easily characterized on the evaluation board ...
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... EVALUATION BOARD SOFTWARE A GUI .exe file for Microsoft® Windows® is included on the CD that ships with the evaluation board. This file allows the user to easily program all the functions on the AD9785/AD9787/AD9788. INTERPOLATION AND FILTER MODE SETTINGS I/Q CHANNEL GAIN MATCHING Figure 80 shows this user interface. The most important features for configuring the AD9785/AD9787/AD9788 are called out in the figure ...
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... AD9785/AD9787/AD9788 EVALUATION BOARD SCHEMATICS Figure 81. Evaluation Board, Power Supply and Decoupling Rev Page 07098-044 RC080 5 5 RC080 ...
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... ACA . 040 2 CC 040 2 CC 040 2 CC 040 2 ACA .7U F Rev Page AD9785/AD9787/AD9788 RC 060 060 040 2 CC 040 2 CC 040 2 CC 040 2 CC 040 2 ...
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... AD9785/AD9787/AD9788 DNP RC0603 R24 PAD DNP RC0603 RC0603 R23 Figure 83. Evaluation Board, ADL5372 (FMOD2) Quadrature Modulator Rev Page 07098-046 100PF C73 C54 100PF C53 ETC1-1-13 100PF ...
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... RC040 2 RC040 2 RC040 2 RC040 2 2 CC040 2 CC040 2 RC040 Figure 84. Evaluation Board, TxDAC Clock Interface Rev Page AD9785/AD9787/AD9788 ...
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... AD9785/AD9787/AD9788 Figure 85. Evaluation Board, Digital Input Data Lines Rev Page 07098-048 ...
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... Figure 86. Evaluation Board, On-Board Power Supply Rev Page AD9785/AD9787/AD9788 07098-049 ...
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... AD9787BSVZ −40C to +85C 1 AD9787BSVZRL −40C to +85C AD9788BSVZ 1 −40C to +85C 1 AD9788BSVZRL −40C to +85C 1 AD9785-EBZ 1 AD9787-EBZ 1 AD9788-EBZ 1 RoHS Compliant Part. 16.00 BSC SQ 14.00 BSC SQ 100 PIN 1 TOP VIEW (PINS DOWN 1.05 1 ...
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... NOTES AD9785/AD9787/AD9788 Rev Page ...
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... AD9785/AD9787/AD9788 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07098-0-2/09(A) Rev Page ...