AD9783 Analog Devices, AD9783 Datasheet
AD9783
Specifications of AD9783
Related parts for AD9783
AD9783 Summary of contents
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... Trademarks and registered trademarks are the property of their respective owners. LVDS Interface, 500 MSPS DACs AD9780/AD9781/AD9783 GENERAL DESCRIPTION The AD9780/AD9781/AD9783 include pin-compatible, high dynamic range, dual digital-to-analog converters (DACs) with 12-/14-/16-bit resolutions, and sample rates 500 MSPS. The devices include specific features for direct conversion transmit ...
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... AD9780/AD9781/AD9783 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 4 AC Specifications .......................................................................... 4 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 18 Serial Peripheral Interface ......................................................... 18 REVISION HISTORY 6/08— ...
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... V × × I 440 Rev Page AD9780/AD9781/AD9783 = 20 mA maximum sample rate, unless OUTFS AD9783 Typ Max Min Typ Max 14 16 ±0.5 ±2 ±1 ±4 0 +0.001 –0.001 0 +0.001 ±2 ±2 20.2 31.66 8.66 20.2 31.66 +1.0 –1.0 +1 0.04 0.04 100 100 30 ...
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... OUTFS Min Typ Max 400 800 1600 300 400 500 500 40 12.5 12.5 800 1600 −100 +100 20 80 120 500 = 20 mA, maximum sample rate, unless OUTFS AD9781 AD9783 Max Min Typ Max Min Typ 61.5 66 −162 −165 − ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −0 DVDD33 + 0.3 V ESD CAUTION −0 CVDD18 + 0.3 V –0 DVDD33 + 0.3 V +125°C −65°C to +150°C Rev Page AD9780/AD9781/AD9783 θ Unit JA 25 °C/W ...
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... AD9780/AD9781/AD9783 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 6. AD9780 Pin Function Descriptions Pin No. Mnemonic 1, 6 CVDD18 2, 5 CVSS 3, 4 CLKP, CLKN 7, 28, 48 DVSS 8, 47 DVDD18 D11P, D11N to D0P, D0N 25, 26 DCOP, DCON 27 DVDD33 29, 30 DCIP, DCIN SDO ...
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... Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. DAC Current Output. Full-scale current is sourced when all data bits are 1s. The heat sink pad on the bottom of the package should be soldered to the PCB plane that carries AVSS. Rev Page AD9780/AD9781/AD9783 54 FS ADJ RESET 53 ...
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... AD9780/AD9781/AD9783 CVDD18 CVDD18 DVDD18 NOTES 1. EXPOSED PAD MUST BE Table 8. AD9783 Pin Function Descriptions Pin No. Mnemonic 1, 6 CVDD18 2, 5 CVSS 3, 4 CLKP, CLKN 7, 28, 48 DVSS 8, 47 DVDD18 D15P, D15N to D0P, D0N 25, 26 DCOP, DCON 27 DVDD33 29, 30 DCIP, DCIN 49 SDO ...
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... Rev Page AD9780/AD9781/AD9783 0 0 16,384 32,768 49,152 CODE Figure 8. AD9783 DNL 85° 16,384 32,768 49,152 CODE Figure 9. AD9783 DNL 25° 16,384 32,768 49,152 CODE Figure 10. AD9783 DNL − ...
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... AD9780/AD9781/AD9783 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 0 4096 8192 CODE Figure 11. AD9781 INL 85° 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 CODE Figure 12. AD9781 INL −40° 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 0 1024 2048 CODE Figure 13. AD9780 INL − ...
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... MSPS 100 350 400 450 500 Figure 20. AD9783 SFDR vs. f 100 30mA 175 200 225 250 Figure 21. AD9783 IMD vs 25°C, at 500 MSPS A 100 175 200 225 250 Figure 22. AD9783 IMD vs. f Rev Page AD9780/AD9781/AD9783 +25° ...
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... Over f OUT 180 210 240 = 25°C, at Figure 26. AD9783 Eight-Tone NSD vs 180 210 240 Figure 27. AD9783 One-Tone NSD vs. f 350 400 450 500 Baseband and Mix Modes, Figure 28. AD9783 Eight-Tone NSD vs. f DAC Rev Page –140 –143 –146 –149 – ...
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... Figure 32. AD9783 ACLR for First Adjacent Channel Two-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, 491.52MSPS 400 500 Figure 33. AD9783 ACLR for Second Adjacent Channel Two-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, 491.52MSPS 400 500 Figure 34 ...
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... OUT Figure 37. AD9783 ACLR for Third Adjacent Channel Four-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 – ...
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... Baseband and Mix OUT Rev Page AD9780/AD9781/AD9783 –50 –55 –60 FIRST ADJACENT –65 CHANNEL –70 –75 –80 SECOND ADJACENT –85 CHANNEL –90 0 100 200 300 ...
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... AD9780/AD9781/AD9783 100 100 150 200 250 300 f (MHz) OUT Figure 47. AD9780 SFDR vs Baseband and Mix Modes, at 500 MSPS, OUT 100 100 150 200 250 ...
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... IF frequency. These images usually waste transmitter power and system bandwidth. By placing the real MIN MAX part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev Page AD9780/AD9781/AD9783 ...
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... GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to any communication cycle with the AD9780/AD9781/AD9783: Phase 1 and Phase 2. Phase 1 is the instruction cycle, which writes an instruction byte into the device. This byte provides the serial port controller with information regarding Phase 2 of the communication cycle: the data transfer cycle ...
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... SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. AD9780/AD9781/AD9783 Serial Port Data I/O (SDIO) Data is always written into the device on this pin. However, SDIO can also function as a bidirectional data output line. The configuration of this pin is controlled by Register 0x00, Bit 7 ...
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... AD9780/AD9781/AD9783 SPI REGISTER MAP Table 11. Register Name Addr Default SPI Control 0x00 0x00 Data Control 0x02 0x00 Power-Down 0x03 0x00 Setup and Hold 0x04 0x00 Timing Adjust 0x05 0x00 Seek 0x06 0x00 Mix Mode 0x0A 0x00 DAC1 FSC 0x0B 0xF9 DAC1 FSC MSBs ...
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... DAC2. DAC1 full-scale 10-bit adjustment word. 0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA. 0x200, sets DAC full-scale output current to the nominal value of 20.0 mA. 0x000, sets DAC full-scale output current to the minimum value of 8.66 mA. Rev Page AD9780/AD9781/AD9783 ...
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... AD9780/AD9781/AD9783 Register Address Bit Name AUXDAC1 0x0D 7:0 AUXDAC1[9:0] 0x0E 1:0 0x0E 7 AUX1SGN 6 AUX1DIR DAC2 FSC 0x0F 7:0 DAC2FSC[9:0] 0x10 1:0 AUXDAC2 0x11 7:0 AUXDAC2[9:0] 0x12 1:0 0x12 7 AUX2SGN 6 AUX2DIR BIST Control 0x1A 7 BISTEN 6 BISTRD 5 BISTCLR BIST Result 1 0x1B 7:0 BISTRES1[15:0] 0x1C 7:0 BIST Result 2 0x1D 7:0 BISTRES2[15:0] 0x1E 7:0 Hardware Version ...
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... CSB should be held high. For applications without a controller, the AD9780/AD9781/ AD9783 also supports pin mode operation, which allows some functional options to be pin selected without the use of the SPI port. Pin mode is enabled anytime the RESET pin is held high. ...
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... LVDS signals, DCO, DCI, and data lines (D[15:0]), as shown in Figure 56. DCO is the output clock generated by the AD9780/AD9781/AD9783 that is used to clock out the data from the digital data engine. The data lines transmit the multip- lexed I and Q data words for the I and Q DACs, respectively. ...
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... Table 14 Rev Page AD9780/AD9781/AD9783 ), the configuration should be tested to verify that + 1 and SMP − 1. Also, it should be OPTIMAL OPTIMAL ...
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... CVDD18 1kΩ 1nF 0.1µF 1nF 287Ω CGND Figure 61. DAC CLK VCM Generator Circuit is equal (86.6 + (0.220 × DAC gain)) × 1000/R FS AD9783 I DAC GAIN 1.2V BAND GAP I DAC REFIO CURRENT FS ADJ SCALING Q DAC 10kΩ Q DAC GAIN Figure 62. Reference Circuitry CLKP ...
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... Figure 65. Switching between the analog modes reshapes the sinc roll-off inherent at the DAC output. This ability to change modes in the AD9780/AD9781/ AD9783 makes the parts suitable for direct IF applications. The user can place a carrier anywhere in the first three Nyquist (5) zones depending on the operating mode selected ...
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... Figure 65. Transfer Function for Each Analog Operating Mode Auxiliary DACs Two auxiliary DACs are provided on the AD9780/AD9781/ AD9783. A functional diagram is shown in Figure 66. The auxiliary DACs are current output devices with two output pins, AUXP and AUXN. The active pin can be programmed to either source or sink current ...
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... Figure 72. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply, 0.200 0.175 0.150 0.125 0.100 0.075 0.050 0.025 400 500 Figure 73. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply, Rev Page AD9780/AD9781/AD9783 0 0 100 200 300 CLOCK SPEED (MSPS) Figure 71. Power Dissipation, I and Q Data, Dual DAC Mode DVDD18 CVDD 0 0 100 ...
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... AD9780/AD9781/AD9783 EVALUATION BOARD SCHEMATICS Figure 74. Power Distribution Rev Page 06936-077 ...
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... R0805 R0805 R0805 R0805 R0805 Figure 75. SPI Interface Rev Page AD9780/AD9781/AD9783 06936-078 ...
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... AD9780/AD9781/AD9783 CLKP CLKN R0402 R0402 R0402 R0402 1 CVDD18 2 CVSS 3 CLKP 4 CLKN 5 CVSS 6 CVDD18 7 DVSS 8 DVDD18 9 D13P 10 D13N 11 D12P 12 D12N 13 D11P 14 D11N 15 D10P 16 D10N 17 D9P 18 D9N Figure 76. Main Schematic Rev Page 06936-079 54 FS ADJ 53 RESET 52 CSB 51 SCLK 50 SDIO 49 SDO 48 DVSS 47 DVDD18 ...
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... G21 S20 S19 G20 G19 S18 S17 G18 G17 S16 S15 G16 G15 S14 S13 G14 G13 S12 S11 G12 G11 S10 S9 G10 Jack G1 Figure 77. Data Input Detail Rev Page AD9780/AD9781/AD9783 06936-080 ...
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... AD9780/AD9781/AD9783 06936-081 R0402 R0402 C0402 C0402 R0402 R0402 R0402 Figure 78. AUX DAC and Clock Input Circuit Details Rev Page ...
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... Very Thin Quad (CP-72-1) Dimensions shown in millimeters Package Description 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ Evaluation Board Evaluation Board Evaluation Board Rev Page AD9780/AD9781/AD9783 0.60 0.42 0.24 55 PIN INDICATOR (BOTTOM VIEW) 4.70 EXPOSED BSC SQ PAD ...
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... AD9780/AD9781/AD9783 NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06936-0-6/08(A) Rev Page ...