AD5371 Analog Devices, AD5371 Datasheet
AD5371
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AD5371 Summary of contents
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... OUTPUT BUFFER AND 14 POWER-DOWN DAC 7 CONTROL VREF2 SUPPLIES GROUP 2 TO GROUP 4 GROUP 2 TO GROUP 4 ARE SAME AS GROUP 1 SIGGND2 SIGGND3 SIGGND4 ©2007–2008 Analog Devices, Inc. All rights reserved. AD5371 VREF0 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 SIGGND0 VREF1 VOUT8 VOUT9 ...
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... AD5371 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Performance Specifications......................................................... 4 AC Characteristics........................................................................ 5 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 13 Terminology .................................................................................... 15 Theory of Operation ...................................................................... 16 DAC Architecture....................................................................... 16 Channel Groups.......................................................................... 16 A/B Registers and Gain/Offset Adjustment............................ 17 Load DAC ...
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... V AD5379 14 ±8.75 V The AD5371 has a high speed serial interface that is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds MHz. It also has a 100 MHz low voltage differential signaling (LVDS) serial interface. ...
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... AD5371 SPECIFICATIONS PERFORMANCE SPECIFICATIONS open circuit; gain (M), offset (C), and DAC offset registers at default values; temperature range for the AD5371 is −40°C to +85°C; all L specifications unless otherwise noted. MIN MAX Table 2. Parameter ACCURACY Resolution ...
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... VREF0, VREF1, VREF2 = 2 V p-p, 1 kHz 20 nV-s 0.2 nV-s 0.02 nV-s Effect of input bus activity on DAC output under test 250 nV/√ REF Rev Page AD5371 1 Test Conditions/Comments GND; normal operating conditions Outputs unloaded, DAC outputs = 0 V Outputs unloaded, DAC outputs = full scale ...
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... AD5371 TIMING CHARACTERISTICS open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T L Table 4. SPI Interface Parameter Limit MIN MAX ...
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... Figure 4. SPI Write Timing Rev Page 200µ (MIN) – PIN 50pF 200µ Figure 3. Load Circuit for SDO Timing Diagram AD5371 (MAX) ...
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... AD5371 SCLK SYNC SDI DB23 SDO SYNC SYNC t 3 SCLK SCLK MSB D23 SDI SDI DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ DB0 DB23 SELECTED REGISTER DATA CLOCKED OUT LSB FROM PREVIOUS WRITE Figure 5. SPI Read Timing ...
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... 0 ESD CAUTION −0 0 −0 +5 − − −0 +0.3 V −40°C to +85°C −65°C to +150°C 130°C 38.72°C/W 40°C/W 230°C 10 sec to 40 sec Rev Page AD5371 ...
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... CONNECT PIN 1 AD5371 TOP VIEW (Not to Scale Figure 7. 80-Lead LQFP Pin Configuration Rev Page VOUT4 59 ...
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... Rev Page LDAC CLR NC AGND A RESET BUSY TESTI AGND B AGND AGND C AGND VOUT25 VOUT26 D V VOUT24 VOUT27 SIGGND3 SS V VOUT28 VOUT30 VOUT29 VOUT32 VOUT31 J SS VOUT34 VOUT33 K VOUT38 V VOUT35 L SIGGND4 SS VREF1 VOUT37 VOUT36 AD5371 ...
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... AD5371 Pin No. Ball No. Mnemonic 58 D11 SIGGND0 31 L7 SIGGND1 41 L12 SIGGND2 7 F1 SIGGND3 16 L3 SIGGND4 52 G12 VREF0 21 M4 VREF1 50 H11 VREF2 19 J9, L11 M12 20, 45 E4, F4, G4, H4 J4, L2, M1 64, 76 A11, A12 DGND 65, 75 A10, B10 SYNC 67 B9 ...
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... DD VREF = +4.096V TIME (µs) Figure 12. Analog Crosstalk Due to LDAC T = 25° –15V +15V DD VREF = +4.096V TIME (µs) Figure 13. Digital Crosstalk 0 0 4096 8192 12288 DAC CODE Figure 14. Typical DNL Plot AD5371 16383 ...
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... AD5371 600 500 400 300 200 100 FREQUENCY (Hz) Figure 15. Output Noise Spectral Density 0. –12V +12V DD VREF = +3V 0. +5.5V CC 0.40 0. +2.5V CC 0.30 0.25 –40 – TEMPERATURE (°C) Figure 16. DI vs. Temperature CC 14 13 –12V +12V DD VREF = +3V 12.0 –40 – TEMPERATURE (°C) Figure 17 ...
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... Output noise spectral density is a measure of internally gener- ated random noise. Random noise is characterized as a spectral density (voltage per √Hz measured by loading all DACs to midscale and measuring noise at the output measured in nV/√Hz. terminals are SS Rev Page AD5371 ...
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... The nominal output span with reference and 20 V with reference. CHANNEL GROUPS The 40 DAC channels of the AD5371 are arranged into five groups of eight channels. The eight DACs of Group 0 derive their reference voltage from VREF0. The eight DACs of Group 1 derive their reference voltage from VREF1 ...
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... Group 0, Group 1, or Group 2 to Group unipolar positive, unipolar negative, or bipolar, either symmet- rical or asymmetrical about 0 V. The DACs in the AD5371 are factory trimmed with the offset DACs set at their default values. This results in optimum offset and gain performance for the default output range and span ...
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... ZERO-SCALE ERROR –4V Figure 23. DAC Transfer Function The output voltage of a DAC in the AD5371 is dependent on the value in the input register, the value of the M and C registers, and the value in the offset DAC. The input code is the value in the X1A or X1B register that is applied to the DAC (X1A, X1B default code = 5461). DAC_CODE = INPUT_CODE × ...
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... These limitations can be overcome by increasing the reference value. With reference span is achieved. The ideal voltage range for the AD5371 is − Using a +3.1 V reference increases the range to −4.133 V to +8.2667 V. Clearly, in this case, the offset and gain errors are insignificant, and the M and C registers can be used to raise the negative voltage to − ...
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... AD5371 enters a thermal shutdown mode that is equivalent to setting the power-down bit in the control register indicate that the AD5371 has entered thermal shutdown mode, Bit 4 of the control register is set to 1. The AD5371 remains in thermal shutdown mode, even if the die temperature falls, until Bit 1 in the control register is cleared to 0 ...
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... TOGGLE MODE The AD5371 has two X2 registers per channel, X2A and X2B, that can be used to switch the DAC output between two levels with ease. This approach greatly reduces the overhead required by a microprocessor, which would otherwise need to write to each channel individually. When the user writes to the X1A, X1B register, the calculation engine takes a certain amount of time to calculate the appropriate X2A or X2B value ...
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... If a continuous clock is used, SYNC must be taken high before th the 25 AD5371. If more than 24 falling clock edges are applied before SYNC is taken high again, the input data becomes corrupted externally gated clock of exactly 24 pulses is used, SYNC can be taken high any time after the 24 The input register addressed is updated on the rising edge of SYNC ...
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... X2A, X2B, and DAC data registers. To read back a register first necessary to tell the AD5371 which register read. This is achieved by writing a word whose first two bits are the Special Function Code 00 to the device ...
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... AD5371 Table 15 shows which groups and which channels are addressed for every combination of Address Bit A5 to Address Bit A0. Table 15. Group and Channel Addressing Address Bit A2 to Address Bit A0 000 001 000 All groups, Group 0, all channels Channel 0 000 Group 0, Group 0, all channels ...
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... Write data A/B Select Register 3. Write data A/B Select Register 4. Block write to A/B select registers Write all 0s (all channels use the X2A register Write all 1s (all channels use the X2B register). Rev Page AD5371 ...
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... AD5371 Table 18. Address Codes for Data Readback F15 F14 F13 F12 Bit F6 to Bit F0 are don’t cares for the data readback function. ...
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... Design the PCB on which the AD5371 is mounted so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5371 system where multiple devices require an AGND-to-DGND connection, make the connection at one point only. Establish the star ground point as close as possible to the device ...
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... AD5371BSTZ-REEL −40°C to +85°C 1 AD5371BBCZ −40°C to +85°C 1 AD5371BBCZ-REEL −40°C to +85°C 1 EVAL-AD5371EBZ RoHS Compliant Part. ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...