AD9776A Analog Devices, AD9776A Datasheet
AD9776A
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AD9776A Summary of contents
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... Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters AD9776A/AD9778A/AD9779A GENERAL DESCRIPTION The AD9776A/AD9778A/AD9779A are dual, 12-/14-/16-bit, high dynamic range digital-to-analog converters (DACs) that provide a sample rate of 1 GSPS, permitting a multicarrier generation up to the Nyquist frequency. They include features optimized for direct conversion transmission applications, including complex digital modulation and gain and offset compensation ...
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... Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 16 Terminology .................................................................................... 24 Theory of Operation ...................................................................... 25 Differences Between AD9776/AD9778/ AD9779 and AD9776A/AD9778A/AD9779A............................................... 25 3-Wire Interface .............................................................................. 26 General Operation of the Serial Interface ............................... 26 Instruction Byte .......................................................................... 26 Serial Interface Port Pin Descriptions ..................................... 27 MSB/LSB Transfers..................................................................... 27 3-Wire Interface Register Map ...................................................... 28 Interpolation Filter Architecture ...
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... Added Table 26 ................................................................................ 41 Changes to Internal Reference Section......................................... 43 Changed Transmit Path Gain and Offset Correction Heading to Gain and Offset Correction ...................................................... 44 Changes to I/Q Channel Gain Matching Section ....................... 44 AD9776A/AD9778A/AD9779A Changes to Auxiliary DAC Operation Section ........................... 44 Replaced Figure 79 .......................................................................... 45 Deleted Figure 79; Renumbered Sequentially ............................. 41 Changes to LO Feedthrough Compensation Section ................. 45 Changes to Table 28 ...
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... AD9776A/AD9778A/AD9779A DELAY SYNC_O LINE SYNC_I DELAY DATACLK LINE DATA ASSEMBLER I P1D[15:0] LATCH 2× Q LATCH 2× P2D[15:0] PERIPHERAL AD9779A FUNCTIONAL BLOCK DIAGRAM CLOCK GENERATION/DISTRIBUTION 2× 2× × /8 DAC ... 7 2× 2× DIGITAL CONTROLLER SERIAL POWER-ON RESET INTERFACE Figure 2. AD9779A Functional Block Diagram Rev ...
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... Rev Page AD9776A/AD9778A/AD9779A = 20 mA, maximum sample rate, unless AD9779A Max Min Typ Max Unit 16 Bits ±2.1 LSB ±6.0 LSB +0.001 −0.001 0 +0.001 % FSR ±2 % FSR 31 ...
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... AD9776A/AD9778A/AD9779A DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input V Logic High IN Input V Logic Low IN Maximum Input Data Rate at Interpolation 1× ...
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... Specified values are with PLL disabled. Timing vs. temperature and data valid keep out windows (that is, the minimum amount of time valid data must be presented to the device to ensure proper sampling) are delineated in Table 28. 2 Measured from CSB rising edge when Register 0x00, Bit 4, is written from with the VREF decoupling capacitor equal to 0.1 μF. AD9776A/AD9778A/AD9779A Min Typ 3.0 − ...
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... DAC OUT W-CDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER f = 491.52 MSPS 100 MHz DAC OUT f = 491.52 MSPS 200 MHz DAC OUT = 20 mA, maximum sample rate, unless OUTFs AD9776A AD9778A Min Typ Max Min Typ ...
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... V to Package Type DVDD33 + 0.3 V 100-Lead TQFP −0 CVDD18 + 0.3 V EPAD Soldered −0 EPAD Not Soldered DVDD33 + 0.3 V ESD CAUTION +125°C −65°C to +150°C Rev Page AD9776A/AD9778A/AD9779A are specified for a 4-layer board in still air. JC θ θ θ 19.1 12.4 7.1 27.4 . ...
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... CONNECT NOTES 1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE. Table 7. AD9776A Pin Function Descriptions Pin No. Mnemonic Description 1 CVDD18 1 ...
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... Digital Ground. 65 PLL_LOCK PLL Lock Indicator. 66 SDO 3-Wire Interface Port Data Output. 67 SDIO 3-Wire Interface Port Data Input/Output. 68 SCLK 3-Wire Interface Port Clock. AD9776A/AD9778A/AD9779A Pin No. Mnemonic Description 69 CSB 3-Wire Interface Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request. ...
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... AD9776A/AD9778A/AD9779A 100 CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND 4 REFCLK+ 5 REFCLK– 6 CGND 7 CGND 8 CVDD18 9 CVDD18 10 CGND 11 AGND 12 SYNC_I+ 13 SYNC_I– 14 DGND 15 DVDD18 16 P1D13 17 P1D12 18 P1D11 19 P1D10 20 P1D9 21 DGND 22 DVDD18 23 P1D8 ...
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... Interface Port Data Output. 67 SDIO 3-Wire Interface Port Data Input/Output. 68 SCLK 3-Wire Interface Port Clock. 69 CSB 3-Wire Interface Port Chip Select Bar. 70 RESET Reset, Active High. AD9776A/AD9778A/AD9779A Pin No. Mnemonic Description 71 IRQ Interrupt Request. 72 AGND Analog Ground. 73 IPTAT Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 μ ...
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... AD9776A/AD9778A/AD9779A 100 CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND 4 REFCLK+ 5 REFCLK– 6 CGND 7 CGND 8 CVDD18 9 CVDD18 10 CGND 11 AGND 12 SYNC_I+ 13 SYNC_I– 14 DGND 15 DVDD18 16 P1D15 17 P1D14 18 P1D13 19 P1D12 20 P1D11 21 DGND 22 DVDD18 23 P1D10 ...
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... Interface Port Data Output. 67 SDIO 3-Wire Interface Port Data Input/Output. 68 SCLK 3-Wire Interface Port Clock. 69 CSB 3-Wire Interface Port Chip Select Bar. 70 RESET Reset, Active High. AD9776A/AD9778A/AD9779A Pin No. Mnemonic Description 71 IRQ Interrupt Request. 72 AGND Analog Ground. 73 IPTAT Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 μ ...
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... AD9776A/AD9778A/AD9779A TYPICAL PERFORMANCE CHARACTERISTICS –1 –2 –3 –4 –5 –6 0 10k 20k 30k 40k CODE Figure 6. AD9779A Typical INL 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 10k 20k 30k 40k CODE Figure 7. AD9779A Typical DNL 100 160MSPS DATA 80 f DATA 70 60 ...
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... OUT 100 100MSPS OUT Rev Page AD9776A/AD9778A/AD9779A PLL OFF PLL (MHz) OUT Figure 15. AD9779A In-Band SFDR vs OUT 4× Interpolation 100 MSPS, PLL On/Off DATA 0dBFS –3dBFS –6dBFS (MHz) OUT Figure 16 ...
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... AD9776A/AD9778A/AD9779A 100 f = 160MSPS DATA 250MSPS 80 DATA (MHz) OUT Figure 18. AD9779A Third-Order IMD vs. f 1× Interpolation 100 f = 160MSPS DATA 200MSPS 70 DATA 100 120 140 160 180 200 220 f (MHz) OUT Figure 19. AD9779A Third-Order IMD vs. f 2× ...
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... STOP 400.0MHz = 30 MHz f Over Output Frequency for Eight-Tone Input with 500 kHz Spacing, DAC Rev Page AD9776A/AD9778A/AD9779A *ATTEN 20dB EXT REF DC-COUPLED STOP 400.0MHz VBW 20kHz SWEEP 1.203s (601 pts) Figure 27. AD9779A Two-Tone Spectrum, = 100 MSPS MHz, 35 MHz ...
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... AD9776A/AD9778A/AD9779A –150 –154 f = 200MSPS DAC –158 f DAC –162 f = 800MSPS DAC –166 –170 (MHz) OUT Figure 30. AD9779A Noise Spectral Density vs Over Output Frequency with a Single-Tone Input at −6 dBFS DAC –55 –60 0dBFS, PLL ENABLED –65 0dBFS, PLL DISABLED –70 – ...
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... REF –25.39dBm *AVG log 10dB PAVG CENTER 143.88MHz *RES BW 30kHz 320 360 400 RMS RESULTS CARRIER POWER –12.74dBm/ 3.84000MHz f DATA Rev Page AD9776A/AD9778A/AD9779A f = 200MSPS DATA f = 160MSPS DATA f = 250MSPS DATA (MHz) OUT Figure 39. AD9778A In-Band SFDR vs OUT 2× ...
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... OUT Figure 46. AD9776A IMD vs. f OUT 4× Interpolation 100 160MSPS DATA 250MSPS DATA 200MSPS DATA (MHz) OUT Figure 47. AD9776A In-Band SFDR vs. f 2× Interpolation 3584 4096 4× 200MSPS 320 360 400 , 80 100 , OUT ...
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... OUT Figure 50. AD9776A Noise Spectral Density vs 200 MSPS DATA f = 200MSPS DAC f = 400MSPS DAC f = 800MSPS DAC (MHz) OUT Figure 51. AD9776A Noise Spectral Density vs. f Single-Tone Input at −6 dBFS 200 MSPS DATA 90 100 , OUT 90 100 , OUT ...
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... AD9776A/AD9778A/AD9779A TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. ...
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... V p-p. PLL Lock Ranges The individual lock ranges for the AD9776A/AD9778A/AD9779A PLL are wider than those for the AD9776/AD9778/AD9779. Table 10. Register Value Differences Between AD9776/AD9778/AD9779 and AD9776A/AD9778A/AD9779A PLL Loop Bandwidth, Part No. Register 0x0A, Bits[4:0] AD9776/AD9778/AD9779 ...
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... Figure 52. 3-Wire Interface Port GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases of a communication cycle with the AD9776A/AD9778A/AD9779A. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coinciding with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle ...
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... The serial port internal byte address genera- tor increments for each byte of the multibyte communication cycle. AD9776A/AD9778A/AD9779A The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first format is active ...
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... AD9776A/AD9778A/AD9779A 3-WIRE INTERFACE REGISTER MAP Note that all unused register bits should be kept at the device default values. Table 13. Address Register Name Hex Decimal Bit 7 Comm 0x00 00 SDIO bidirectional Digital 0x01 01 Interpolation Factor[1:0] Control 0x02 02 Data format Sync 0x03 03 DATACLK Control delay mode ...
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... Inverts the polarity of Pin 39, the TXENABLE input pin (also functions as IQSELECT). Q first 0: in interleaved mode, the I data precedes the Q data on the input port interleaved mode, the Q data precedes the I data on the input port. Rev Page AD9776A/AD9778A/AD9779A Default 0000 ...
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... AD9776A/AD9778A/AD9779A Register Register Name Address Bits Sync Control 0x03 7 0x03 6 0x03 5:4 0x03 3:0 0x04 7:4 0x04 3:1 0x04 0 0x05 7:4 0x05 3:1 0x05 0 0x06 7:4 0x06 3:0 0x07 7 0x07 6 0x07 5 0x07 4:0 Parameter Function DATACLK delay mode 0: manual data timing error detect mode. 1: automatic data timing error detect mode. ...
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... The Q DAC Gain Adjustment[9:0] value is the Q DAC 10-bit gain setting word. Bit 9 is the MSB and Bit 0 Q DAC Gain Adjustment[7:0] is the LSB. Q DAC sleep 0: Q DAC on DAC off. Q DAC power-down 0: Q DAC on DAC off. Rev Page AD9776A/AD9778A/AD9779A /f . VCO DACCLK / DACCLK / DACCLK / ...
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... AD9776A/AD9778A/AD9779A Register Register Name Address Bits AUX DAC2 Control 0x12 1:0 0x11 7:0 0x12 7 0x12 6 0x12 5 0x13 to 0x18 Interrupt 0x19 7 0x19 6 0x19 4 0x19 3 0x19 2 0x19 0 Version 0x1F 7:0 Parameter Function Auxiliary DAC2 Data[9:8] Auxiliary DAC2 Data[9:0] is the 10-bit output current control word. Magnitude of the auxiliary Auxiliary DAC2 Data[7:0] DAC current increases with increasing value ...
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... INTERPOLATION FILTER ARCHITECTURE The AD9776A/AD9778A/AD9779A can provide up to 8× inter- polation, or the interpolation filters can be entirely disabled important to note that the input signal should be backed off by approximately 0.01 dB from full scale to avoid overflowing the interpolation filters. The coefficients of the low-pass filters and the inverse sinc filter are given in Table 15, Table 16, Table 17, and Table 18 ...
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... AD9776A/AD9778A/AD9779A 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –4 –3 –2 – (× Input Data Rate) OUT Figure 58. 4× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off –10 –20 – ...
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... The shifted mode capability allows the filter pass band to be placed anywhere in the DAC Nyquist bandwidth. The AD9776A/AD9778A/AD9779A are dual DACs with internal complex modulators built into the interpolating filter response. In dual channel mode, the devices expect the real and ...
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... AD9776A/AD9778A/AD9779A Table 19. Interpolation Filter Modes, (Register 0x01, Bits[5:2]) Interpolation Filter Modulation Factor[7:6] Mode[5:2] 8 0x00 8 0x01 8 0x02 8 0x03 8 0x04 8 0x05 8 0x06 8 0x07 8 0x08 8 0x09 8 0x0A 8 0x0B 8 0x0C 8 0x0D 8 0x0E 8 0x0F 4 0x00 4 0x01 4 0x02 4 0x03 4 0x04 4 0x05 4 0x06 4 0x07 2 0x00 2 0x01 2 0x02 2 0x03 ...
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... INTERPOLATION FILTER BANDWIDTH LIMITS The AD9776A/AD9778A/AD9779A use a novel interpolation filter architecture that allows DAC IF frequencies to be gener- ated anywhere in the spectrum. Figure 68 shows the traditional choice of DAC IF output bandwidth placement. Note that there are no possible filter modes in which the carrier can be placed near 0.5 × ...
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... AD9776A/AD9778A/AD9779A As shown in Table 20, the mixing functions of most of the modes result in cross-coupling of samples between the I and Q channels. The I and Q channels only operate independently with the f /2 mode. This means that real modulation using both S the I and Q DAC outputs can only be done in the f other modulation modes require complex input data and produce complex output signals ...
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... SOURCING THE DAC SAMPLE CLOCK The AD9776A/AD9778A/AD9779A offer two modes of sourcing the DAC sample clock (DACCLK). The first mode employs an on-chip clock multiplier that accepts a reference clock operating at the lower input frequency, most commonly the data input frequency. The on-chip PLL then multiplies the reference clock higher frequency, which can then be used to generate all of the internal clocks required by the DAC ...
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... AD9776A/AD9778A/AD9779A Table 23. Typical VCO Frequency Range vs. PLL Band Select Value PLL Lock Ranges Over Temperature, −40°C to +85°C VCO Frequency Range (MHz) PLL Band Select f LOW 111111 (63) Auto mode 111110 (62) 1975 111101 (61) 1956 111100 (60) 1938 111011 (59) 1923 111010 (58) 1902 111001 (57) ...
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... Set PLL band = readback band 55°C to 85°C Set PLL band = readback band − 1 AD9776A/AD9778A/AD9779A Known Temperature Calibration with Memory If temperature sensing is not available in the system, a factory calibration at a known temperature is another method for guaranteeing lock over temperature. Factory calibration can be performed as follows: 1 ...
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... AD9776A/AD9778A/AD9779A DRIVING THE REFCLK INPUT The REFCLK input requires a low jitter differential drive signal. The signal level can range from 400 mV p-p differential to 1.6 V p-p differential centered about a 400 mV input common- mode voltage. Looking at the single-ended inputs, REFCLK+ or REFCLK−, each input pin can safely swing from 200 mV p-p to 800 mV p-p about the 400 mV common-mode voltage ...
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... R 12 1024 0.1µF in the resistor of is equal to ⎞ ⎞ ⎟ × ⎟ 32 ⎠ ⎠ Rev Page AD9776A/AD9778A/AD9779A AD9776A/AD9778A/AD9779A I DAC GAIN I DAC 1.2V BAND GAP VREF CURRENT I120 SCALING 10kΩ Q DAC Q DAC GAIN Figure 76. Reference Circuitry ...
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... LO compensation. AUXILIARY DAC OPERATION Two auxiliary DACs are provided on the AD9776A/AD9778A/ AD9779A. The full-scale output current on these DACs is derived from the 1.2 V band gap reference and external resistor between the I120 pin and ground. The gain scale from the reference ...
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... DAC being adjusted or adjusting the output current of the other auxiliary DAC. It may take practice before an effective algorithm is achieved. Using the AD9776A/AD9778A/AD9779A evaluation board, the LO feedthrough can typically be adjusted down to the noise floor, although this is not stable over temperature. ...
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... DATACLK signal. The TXENABLE signal must be high to enable the transmit path. INPUT DATA REFERENCED TO DATACLK The simplest method of interfacing to the AD9776A/AD9778A/ AD9779A is when the input data is referenced to the DATACLK output. The DATACLK output is a buffered version (with some fixed delay) of the internal clock that is used to latch the input data ...
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... Rev Page AD9776A/AD9778A/AD9779A t H_SYNC t S_SYNC t SREFCLK t HREFCLK ), but cannot be asserted prior to the previous , and the maximum S_SYNC − DACCLK H_SYNC t DACCLK t H_SYNC t S_SYNC t SREFCLK t HREFCLK × 4 DACCLK REFCLK PLL Enabled Min t (ns) ...
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... AD9776A/AD9778A/AD9779A OPTIMIZING THE DATA INPUT TIMING The AD9776A/AD9778A/AD9779A have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the DATACLK output and DCLK_SMP (the internal clock that samples the input data). This optimization is made by a sequence of 3-wire interface register read and write operations ...
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... If it has increased, continue incrementing the value of SYNC_I delay until the margin is maximized. However, if incrementing the SYNC_I delay reduced the timing margin, then the delay should be reduced until the timing margin is optimized. Rev Page AD9776A/AD9778A/AD9779A . DATACLK SYNC_I Rising Edges Required for Synchronization Pulse 1 (default) ...
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... AD9776A/AD9778A/AD9779A SYNCHRONIZING DEVICES TO A SYSTEM CLOCK The AD9776A/AD9778A/AD9779A offer a pulse mode synchro- nization scheme (see Figure 89) to align the DAC outputs of multiple devices within a system to the same DACCLK edge. The internal clocks are synchronized by providing either a one- time pulse or a periodic signal to the SYNC_I inputs (SYNC_I+, SYNC_I− ...
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... INTERPOLATION 1× INTERPOLATION 175 200 225 250 2× INTERPOLATION 1× INTERPOLATION 175 200 225 250 Figure 96. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC Rev Page AD9776A/AD9778A/AD9779A ALL INTERPOLATION MODES 100 125 150 175 f (MSPS) DATA Includes Modulation Modes and Zero Stuffing 1.0 8× ...
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... DAC Figure 99. DVDD18 Power Dissipation of Inverse Sinc Filter POWER-DOWN AND SLEEP MODES The AD9776A/AD9778A/AD9779A have a variety of power-down modes; thus, the digital engine, main TxDACs, or auxiliary DACs can be powered down individually or together. Via the 3-wire interface port, the main TxDACs can be placed in sleep or power- down mode. In sleep mode, the TxDAC output is turned off, 2× ...
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... GENERATOR CLOCK IN P4 DIGITAL INPUT CONNECTOR Figure 101. AD9776A/AD9778A/AD9779A Evaluation Board Showing All Connections The typical evaluation setup is shown in Figure 100. A sine or square wave clock can be used to source the DAC sample clock. The spectral purity of the clock directly affects the device per- formance ...
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... AD9776A/AD9778A/AD9779A The evaluation board comes with software that allows the user to program the on-chip configuration registers. Via the 3-wire interface port, the devices can be programmed into any of its various operating modes. The default software window is shown in Figure 102. The evaluation board also comes populated with the ADL537x modulator to allow for the evaluation subsystem ...
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... Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Evaluation Board Evaluation Board Evaluation Board Rev Page AD9776A/AD9778A/AD9779A 100 1 BOTTOM VIEW (PINS UP) CONDUCTIVE HEAT SINK ...
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... AD9776A/AD9778A/AD9779A NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06452-0-9/08(B) Rev Page ...