AD5665 Analog Devices, AD5665 Datasheet

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AD5665

Manufacturer Part Number
AD5665
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD5665

Resolution (bits)
16bit
Dac Settling Time
4µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
I2C/Ser 2-wire,Ser

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FEATURES
Low power, smallest pin-compatible, quad nanoDACs
AD5625R/AD5645R/AD5665R
AD5625/AD5665
3 mm × 3 mm 10-lead LFCSP and 14-lead TSSOP
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale/midscale
Per channel power-down
Hardware LDAC and CLR functions
I
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5625R/AD5645R/AD5665R and AD5625/AD5665
members of the nanoDAC® family are low power, quad, 12-/
14-/16-bit, buffered voltage-out DACs with/without an on-chip
reference. All devices operate from a single 2.7 V to 5.5 V supply,
are guaranteed monotonic by design, and have an I
serial interface.
The AD5625R/AD5645R/AD5665R have an on-chip reference.
The LFCSP versions of the AD56x5R have a 1.25 V or 2.5 V,
10 ppm/°C reference, giving a full-scale output range of 2.5 V or
5 V; the TSSOP versions of the AD56x5R have a 2.5 V, 5 ppm/°C
reference, giving a full-scale output range of 5 V. The on-chip
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a software write.
The AD5625/AD5665 require an external reference voltage to
set the output range of the DAC.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (POR = GND) or midscale
(POR = V
on-chip precision output amplifier enables rail-to-rail output swing.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2
C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
12-/14-/16-bit nanoDACs
On-chip, 2.5 V, 5 ppm/°C reference in TSSOP
On-chip, 2.5 V, 10 ppm/°C reference in LFCSP
On-chip, 1.25 V, 10 ppm/°C reference in LFCSP
12-/16-bit nanoDACs
External reference only
DD
) and remains there until a valid write occurs. The
AD5625R/AD5645R/AD5665R, AD5625/AD5665
2
C-compatible
5 ppm/°C On-Chip Reference, I
Quad, 12-/14-/16-Bit nanoDACs with
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
ADDR1
ADDR2
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
The AD56x5R/AD56x5 use a 2-wire I
interface that operates in standard (100 kHz), fast (400 kHz),
and high speed (3.4 MHz) modes.
Table 1. Related Devices
Part No.
AD5025/AD5045/AD5065
AD5624R/AD5644R/AD5664R,
AD5624/AD5664
AD5627R/AD5647R/AD5667R,
AD5627/AD5667
AD5666
ADDR1
ADDR2
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
ADDR2, LDAC, CLR, POR.
SDA
ADDR2, LDAC, CLR, POR.
SCL
SDA
SCL
AD5625R/AD5645R/AD5665R
LDAC CLR
LDAC CLR
FUNCTIONAL BLOCK DIAGRAMS
AD5625/AD5665
Figure 1. AD5625R/AD5645R/AD5665R
V
POWER-ON RESET
V
POWER-ON RESET
©2007-2009 Analog Devices, Inc. All rights reserved.
DD
DD
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
Figure 2. AD5625/AD5665
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
POR
POR
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
GND
GND
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
Description
Dual 12-/14-/16-bit DACs
Quad SPI 12-/14-/16-bit DACs,
with/without internal reference
Dual I
with/without internal reference
Quad SPI 16-bit DAC with
internal reference
2
V
POWER-DOWN LOGIC
POWER-DOWN LOGIC
C-compatible serial
2
REFIN
C 12-/14-/16-bit DACs,
2
STRING
STRING
STRING
STRING
STRING
STRING
STRING
STRING
DAC A
DAC B
DAC C
DAC D
V
DAC A
DAC B
DAC C
DAC D
C Interface
REFIN
/V
REFOUT
1.25V/2.5V REF
BUFFER
BUFFER
BUFFER
BUFFER
www.analog.com
BUFFER
BUFFER
BUFFER
BUFFER
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
A
B
C
D
A
B
C
D

Related parts for AD5665

AD5665 Summary of contents

Page 1

... V. The on-chip reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. The AD5625/AD5665 require an external reference voltage to set the output range of the DAC. The part incorporates a power-on reset circuit that ensures that ...

Page 2

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Specifications—AD5665R/AD5645R/AD5625R ..................... 3 Specifications—AD5665/AD5625 ............................................. 5 AC Characteristics ........................................................................ Timing Specifications ............................................................ 8 Absolute Maximum Ratings .......................................................... 10 ESD Caution ................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 12 Terminology .................................................................................... 20 Theory of Operation ...................................................................... 22 Digital-to-Analog Converter (DAC) ....................................... 22 Resistor String ...

Page 3

... DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range 0.75 Reference Input Impedance REFERENCE OUTPUT (1.25 V) Output Voltage 1.247 3 Reference TC Output Impedance AD5625R/AD5645R/AD5665R, AD5625/AD5665 = 200 pF to GND all specifications T L REFIN DD A Grade B Grade Typ Max Min Typ Max 16 ± ...

Page 4

... Temperature range of A and B grades is −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5665R (Code 512 to Code 65,024), AD5645R (Code 128 to Code 16,256), AD5625R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive ...

Page 5

... LOGIC INPUTS (SDA, SCL Input Current Input Low Voltage INL V , Input High Voltage INH C , Pin Capacitance Input Hysteresis HYST AD5625R/AD5645R/AD5665R, AD5625/AD5665 = 200 pF to GND all specifications T L REFIN DD B Grade Min Typ Max 16 ±8 ±16 ±1 12 ±0.5 ±1 ± ...

Page 6

... DD 1 Temperature range of B grade is −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5665 (Code 512 to Code 65,024), AD5625 (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. ...

Page 7

... Total Harmonic Distortion Output Noise Spectral Density Output Noise 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical @ 25°C. AD5625R/AD5645R/AD5665R, AD5625/AD5665 = 200 pF to GND all specifications T L REFIN DD Min Typ Max ...

Page 8

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 TIMING SPECIFICATIONS 5.5 V; all specifications T DD Table 5. 2 Parameter Test Conditions 3 f Standard mode SCL Fast mode High speed mode 100 pF B High speed mode 400 Standard mode 1 Fast mode High speed mode 100 pF B High speed mode, C ...

Page 9

... Fast mode SP High speed mode 1 See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7 refers to the capacitance on the bus line The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the part ...

Page 10

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 6. Parameter V to GND GND OUT GND REFIN REFOUT Digital Input Voltage to GND Operating Temperature Range, Industrial Storage Temperature Range Junction Temperature (T maximum) J Power Dissipation θ Thermal Impedance JA LFCSP_WD (4-Layer Board) ...

Page 11

... Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register. N/A 6 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 8). EPAD For the 10-lead LFCSP, the exposed pad must be tied to GND. AD5625R/AD5645R/AD5665R, AD5625/AD5665 SCL 14 SDA 13 GND ...

Page 12

... Rev Page REF T = 25° 10k 20k 30k 40k 50k CODE Figure 11. DNL, AD5665, External Reference REF T = 25° 2500 5000 7500 10000 12500 CODE Figure 12. DNL, AD5645R, External Reference ...

Page 13

... 2.5V REFOUT T = 25° –2 –4 –6 –8 –10 CODE Figure 14. INL, AD5665R, 2.5 V Internal Reference 2.5V REFOUT 25° –1 –2 –3 –4 CODE Figure 15. INL, AD5645R, 2.5 V Internal Reference 1 2.5V 0.8 REFOUT T = 25° ...

Page 14

... Rev Page 1.25V REFOUT T = 25°C A CODE Figure 23. DNL, AD5665R,1.25 V Internal Reference 1.25V REFOUT T = 25°C A CODE Figure 24. DNL, AD5645R,1.25 V Internal Reference 1.25V REFOUT T = 25° 500 ...

Page 15

... MAX DNL 0 –2 –4 –6 –8 2.7 3.2 3.7 4.2 4.7 V (V) DD Figure 28. INL Error and DNL Error vs. Supply AD5625R/AD5645R/AD5665R, AD5625/AD5665 0 –0.02 MAX INL –0.04 –0.06 –0.08 –0.10 MIN DNL –0.12 –0.14 –0.16 MIN INL –0.18 –0.20 80 100 –40 Figure 29. Gain Error and Full-Scale Error vs. Temperature 1 ...

Page 16

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 1 25°C A 0.5 ZERO-SCALE ERROR 0 –0.5 –1.0 –1.5 –2.0 –2.5 2.7 3.2 3.7 4.2 V (V) DD Figure 32. Zero-Scale Error and Offset Error vs. Supply (mA) DD Figure 33. I Histogram with External Reference 1.25V V REFOUT REFOUT I (mA) DD Figure 34. I Histogram with Internal Reference DD OFFSET ERROR 4 ...

Page 17

... REFOUT T = 25° FULL SCALE 3/4 SCALE 2 MIDSCALE 1 1/4 SCALE 0 ZERO SCALE –1 –30 –20 – CURRENT (mA) Figure 40. AD56x5R with 1.25 V Reference, Source and Sink Capability AD5625R/AD5645R/AD5665R, AD5625/AD5665 CH1 5. CH3 5.0V Rev Page ...

Page 18

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 2.538 REF 2.537 T = 25°C A 2.536 5ns/SAMPLE NUMBER 2.535 GLITCH IMPULSE = 9.494nV 2.534 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 2.522 2.521 0 50 100 150 200 250 300 SAMPLE NUMBER Figure 44 ...

Page 19

... 25°C A –30 DAC LOADED WITH FULL SCALE ± 0.3V p-p REF –40 –50 –60 –70 –80 –90 –100 FREQUENCY (Hz) Figure 51. Total Harmonic Distortion AD5625R/AD5645R/AD5665R, AD5625/AD5665 –5 –10 –15 –20 –25 –30 –35 –40 ...

Page 20

... DAC register. Ideally, the output should The zero-code error is always positive in the AD5665R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the out- put amplifier. Zero-code error is expressed in millivolts (mV). ...

Page 21

... LDAC low while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nanovolts per second (nV-s). AD5625R/AD5645R/AD5665R, AD5625/AD5665 Multiplying Bandwidth The multiplying bandwidth is a measure of the finite bandwidth of the amplifiers within the DAC. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output ...

Page 22

... GAIN = ×2 V OUT INTERNAL REFERENCE The AD5625R/AD5645R/AD5665R feature an on-chip reference. Versions without the R suffix require an external reference. The on-chip reference is off at power-up and is enabled via a write to a control register. See the Internal Reference Setup section for details. Versions packaged in a 10-lead LFCSP have a 1.25 V reference ...

Page 23

... When writing to the AD56x5R/AD56x5, the user must begin with a start command followed by an address byte ( 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5665 requires two bytes of data for the DAC and a command byte that controls various A1 A0 DAC functions ...

Page 24

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 1 SCL SDA START BY MASTER FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED) SDA DB15 DB14 DB13 DB12 (CONTINUED) 1 SCL SDA START BY MASTER FRAME 1 SLAVE ADDRESS 1 SCL (CONTINUED) SDA DB15 DB14 DB13 DB12 (CONTINUED) 1 SCL SDA START BY ...

Page 25

... All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices return to standard/fast mode. The part also returns to standard/fast mode when CLR is activated while the part is in high speed mode. AD5625R/AD5645R/AD5665R, AD5625/AD5665 ...

Page 26

... Figure 63. Multiple Block Write with Initial Command Byte Only ( D15 D14 D13 D12 D11 D10 DAC DATA DATA HIGH BYTE Figure 64. AD5665R/AD5665 Input Shift Register (16-Bit DAC) A0 D13 D12 D11 D10 D9 D8 DAC DATA DATA HIGH BYTE Figure 65. AD5645R Input Shift Register (14-Bit DAC) ...

Page 27

... DAC All DACs AD5625R/AD5645R/AD5665R, AD5625/AD5665 LDAC FUNCTION The AD56x5R/AD56x5 DACs have double-buffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register, and the digital code is transferred to the relevant input register upon completion of a valid write sequence ...

Page 28

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 Synchronous LDAC The DAC registers are updated after new data is read in. LDAC can be permanently low or pulsed. Asynchronous LDAC The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. ...

Page 29

... DAC ADDRESS COMMAND (DON’T CARE) AD5625R/AD5645R/AD5665R, AD5625/AD5665 Table 14. Modes of Operation for the AD56x5R/AD56x5 DB5 The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power- down is typically 4 μ ...

Page 30

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 POWER-ON RESET AND SOFTWARE RESET The AD56x5R/AD56x5 contain a power-on reset circuit that controls the output voltage during power-up. The 10-lead version of the device powers The 14-lead version has a power-on reset (POR) pin that allows the output voltage to be selected. By connecting the POR pin to GND, the AD56x5R/ AD56x5 output powers ...

Page 31

... This is an output voltage range of ±5 V, with 0x0000 corre- sponding to a −5 V output and 0xFFFF corresponding output. AD5625R/AD5645R/AD5665R, AD5625/AD5665 +5V POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit helpful to carefully consider the power supply and ground return layout on the board. ...

Page 32

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 OUTLINE DIMENSIONS PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 4.50 4.40 4.30 PIN 1 1.05 1.00 0.80 0.15 0.05 COPLANARITY 0.10 0.30 3.00 0.23 BSC SQ 0. EXPOSED (BOTTOM VIEW) 0.50 0.40 5 0.30 TOP VIEW 0.80 MAX 0.55 NOM 0.05 MAX 0.02 NOM 0.20 REF * FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ...

Page 33

... AD5665RBRUZ-1REEL7 −40°C to +105°C AD5665RBRUZ-2 −40°C to +105°C AD5665RBRUZ-2REEL7 −40°C to +105°C EVAL-AD5665REBZ1 EVAL-AD5665REBZ2 RoHS Compliant Part. AD5625R/AD5645R/AD5665R, AD5625/AD5665 On-Chip Maximum 2 Accuracy Reference I C Speed ±1 LSB INL None 400 kHz ±1 LSB INL ...

Page 34

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 NOTES Rev Page ...

Page 35

... NOTES AD5625R/AD5645R/AD5665R, AD5625/AD5665 Rev Page ...

Page 36

... AD5625R/AD5645R/AD5665R, AD5625/AD5665 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06341-0-12/09(B) Rev Page ...

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