AD9743 Analog Devices, AD9743 Datasheet

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AD9743

Manufacturer Part Number
AD9743
Description
Dual 10-Bit 250 MSPS Digital-to-Analog Converters
Manufacturer
Analog Devices
Datasheet

Specifications of AD9743

Resolution (bits)
10bit
Dac Update Rate
250MSPS
Dac Settling Time
n/a
Max Pos Supply (v)
+3.47V
Single-supply
No
Dac Type
Current Out
Dac Input Format
Par

Available stocks

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Part Number
Manufacturer
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Price
Part Number:
AD9743BCPZ
Manufacturer:
ADI
Quantity:
1 235
FEATURES
High dynamic range, dual DACs
Low noise and intermodulation distortion
Single carrier WCDMA ACLR = 80 dBc @ 61.44 MHz IF
Innovative switching output stage permits useable outputs
LVCMOS inputs with dual-port or optional interleaved
Differential analog current outputs are programmable from
Auxiliary 10-bit current DACs with source/sink capability for
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, Pb-free, 72-Lead LFCSP
APPLICATIONS
Wireless infrastructure:
Wideband communications:
Instrumentation:
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
beyond Nyquist frequency
single-port operation
8.6 mA to 31.7 mA full scale
external offset nulling
WCDMA, CDMA2000, TD-SCDMA, WiMAX
LMDS/MMDS, point-to-point
RF signal generators, arbitrary waveform generators
P2D<15:0>
PID<15:0>
CLKN
CLKP
INTERFACE
CMOS
PERIPHERAL
INTERFACE
SERIAL
FUNCTIONAL BLOCK DIAGRAM
AD9741/AD9743/AD9745/AD9746/AD9747
250 MSPS Digital-to-Analog Converters
INTERFACE LOGIC
REFERENCE
INTERNAL
BIAS
AND
10
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The AD9741/AD9743/AD9745/AD9746/AD9747 are pin-
compatible, high dynamic range, dual digital-to-analog
converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions
and sample rates of up to 250 MSPS. The devices include
specific features for direct conversion transmit applications,
including gain and offset compensation, and they interface
seamlessly with analog quadrature modulators, such as the
ADL5370.
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. In addition, some pin-programmable
features are offered for those applications without a controller.
PRODUCT HIGHLIGHTS
1.
2.
3.
OFFSET
OFFSET
GAIN
GAIN
Low noise and intermodulation distortion (IMD) enables
high quality synthesis of wideband signals.
Proprietary switching output for enhanced dynamic
performance.
Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
DAC
DAC
DAC
DAC
Dual 8-/10-/12-/14-/16-Bit
16-BIT
16-BIT
DAC1
DAC2
©2007 Analog Devices, Inc. All rights reserved.
IOUT1P
IOUT1N
IOUT2P
IOUT2N
AUX1P
AUX1N
AUX2P
AUX2N
www.analog.com

Related parts for AD9743

AD9743 Summary of contents

Page 1

... Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters AD9741/AD9743/AD9745/AD9746/AD9747 GENERAL DESCRIPTION The AD9741/AD9743/AD9745/AD9746/AD9747 are pin- compatible, high dynamic range, dual digital-to-analog converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions and sample rates 250 MSPS. The devices include specific features for direct conversion transmit applications, ...

Page 2

... AD9741/AD9743/AD9745/AD9746/AD9747 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 5 Digital and Timing Specifications.............................................. 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 14 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 18 Serial Peripheral Interface ...

Page 3

... SPECIFICATIONS DC SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX sample rate, unless otherwise noted. Table 1. AD9741, AD9743, and AD9745 Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient ...

Page 4

... AD9741/AD9743/AD9745/AD9746/AD9747 AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX sample rate, unless otherwise noted. The AD9745 is repeated in Table 2 so the user can compare it with all other parts. Table 2. AD9745, AD9746, and AD9747 Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) ...

Page 5

... AC SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX sample rate, unless otherwise noted. Table 3. AD9741, AD9743, and AD9745 Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR 250 MSPS MHz DAC OUT f = 250 MSPS MHz DAC OUT 250 MSPS 180 MHz ...

Page 6

... AD9741/AD9743/AD9745/AD9746/AD9747 AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX sample rate, unless otherwise noted. The AD9745 is repeated in Table 4 so the user can compare it with all other parts. Table 4. AD9745, AD9746, and AD9747 Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR 250 MSPS MHz ...

Page 7

... DIGITAL AND TIMING SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX sample rate, unless otherwise noted. Table 5. AD9741/AD9743/AD9745/AD9746/AD9747 Parameter DAC CLOCK INPUTS (CLKP, CLKN) Differential Peak-to-Peak Voltage Single-Ended Peak-to-Peak Voltage Common-Mode Voltage Input Current Input Frequency DATA CLOCK OUTPUT (DCO) ...

Page 8

... AD9741/AD9743/AD9745/AD9746/AD9747 ABSOLUTE MAXIMUM RATINGS Table 6. With Parameter Respect to AVDD33, DVDD33 AVSS DVSS CVSS DVDD18, CVDD18 AVSS DVSS CVSS AVSS DVSS CVSS DVSS AVSS CVSS CVSS AVSS DVSS REFIO AVSS IOUT1P, IOUT1N, IOUT2P, AVSS IOUT2P, AUX1P, AUX1N, AUX2P, AUX2N P1D15 to P1D0, DVSS ...

Page 9

... SCLK 52 CSB 53 RESET 54 FSADJ 55 REFIO 56, 57, 71, 72 AVDD33 58, 61, 64, 67, 70 AVSS 59 IOUT2P 60 IOUT2N 62 AUX2P 63 AUX2N 65 AUX1N 66 AUX1P 68 IOUT1N 69 IOUT1P EPAD AVSS AD9741/AD9743/AD9745/AD9746/AD9747 CVDD18 1 PIN 1 CVSS 2 INDICATOR CLKP 3 CLKN 4 CVSS 5 CVDD18 6 DVSS 7 AD9741 DVDD18 8 P1D7 9 (TOP VIEW) P1D6 10 P1D5 11 P1D4 12 P1D3 13 P1D2 ...

Page 10

... P1D4 14 P1D3 15 P1D2 16 P1D1 17 P1D0 18 Figure 3. AD9743 Pin Configuration Description Clock Supply Voltage (1.8 V). Clock Supply Common (0 V). Differential DAC Clock Input. Complementary Differential DAC Clock Input. Digital Supply Common (0 V). Digital Core Supply Voltage (1.8 V). Port 1 Data Bit Inputs. No Connect. Data Clock Output. Use to clock data source. ...

Page 11

... SCLK 52 CSB 53 RESET 54 FSADJ 55 REFIO 56, 57, 71, 72 AVDD33 58, 61, 64, 67, 70 AVSS 59 IOUT2P 60 IOUT2N 62 AUX2P 63 AUX2N 65 AUX1N 66 AUX1P 68 IOUT1N 69 IOUT1P EPAD AVSS AD9741/AD9743/AD9745/AD9746/AD9747 CVDD18 1 PIN 1 CVSS 2 INDICATOR CLKP 3 CLKN 4 CVSS 5 CVDD18 6 DVSS 7 AD9745 DVDD18 8 P1D11 9 (TOP VIEW) P1D10 10 P1D9 11 P1D8 12 P1D7 13 P1D6 ...

Page 12

... AD9741/AD9743/AD9745/AD9746/AD9747 CONNECT Table 11. AD9746 Pin Function Descriptions Pin No. Mnemonic Description 1, 6 CVDD18 Clock Supply Voltage (1.8 V CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V DVDD18 Digital Core Supply Voltage (1 ...

Page 13

... SCLK 52 CSB 53 RESET 54 FSADJ 55 REFIO 56, 57, 71, 72 AVDD33 58, 61, 64, 67, 70 AVSS 59 IOUT2P 60 IOUT2N 62 AUX2P 63 AUX2N 65 AUX1N 66 AUX1P 68 IOUT1N 69 IOUT1P EPAD AVSS AD9741/AD9743/AD9745/AD9746/AD9747 CVDD18 1 PIN 1 CVSS 2 INDICATOR CLKP 3 CLKN 4 CVSS 5 CVDD18 6 DVSS 7 AD9747 DVDD18 8 P1D15 9 (TOP VIEW) P1D14 10 P1D13 11 P1D12 12 P1D11 13 P1D10 ...

Page 14

... AD9741/AD9743/AD9745/AD9746/AD9747 TYPICAL PERFORMANCE CHARACTERISTICS 100 90 125MSPS 80 250MSPS (MHz) OUT Figure 7. AD9747 SFDR vs Normal Mode OUT 100 125 150 175 200 f (MHz) OUT Figure 8. AD9747 SFDR vs Mix Mode, 250 MSPS OUT 90 85 NORMAL MODE ...

Page 15

... THE DAC CLOCK. SEE INPUT DATA TIMING SECTION (MHz) OUT Figure 15. AD9747 SFDR vs. f Over Input Data Timing OUT AD9741/AD9743/AD9745/AD9746/AD9747 100 100 120 0 Figure 16. AD9747 IMD vs. Analog Output, 250 MSPS 100 ...

Page 16

... Figure 20. ACLR vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS 61.44 MHz CARRIER MIX MODE 175 200 225 250 = 20 mA Figure 21. NSD vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS AD9746 AD9747 Rev Page –130 –135 –140 –145 –150 –155 –160 –165 AD9741 AD9743 AD9745 AD9746 f = 61.44 MHz CARRIER AD9747 CARRIER ...

Page 17

... The range of allowable voltage seen by the analog output of a current output DAC. Operation beyond the compliance limits may cause output stage saturation and/or a breakdown resulting in nonlinear performance. AD9741/AD9743/AD9745/AD9746/AD9747 Temperature Drift Temperature drift is specified as the maximum change in a parameter from ambient temperature (25°C) to either and is typically reported as ppm/° ...

Page 18

... GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to any communication cycle with the AD9741/AD9743/AD9745/AD9746/AD9747: Phase 1 and Phase 2. Phase 1 is the instruction cycle, which writes an instruction byte into the device. This byte provides the serial port controller with information regarding Phase 2 of the communication cycle: the data transfer cycle ...

Page 19

... SCLK. Serial Data I/O (SDIO) Data is always written into the device on this pin. However, SDIO can also function as a bidirectional data output line. AD9741/AD9743/AD9745/AD9746/AD9747 The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, which configures the SDIO pin as unidirectional. ...

Page 20

... AD9741/AD9743/AD9745/AD9746/AD9747 SPI REGISTER MAP Reading any register returns previously written values for all defined register bits, unless otherwise noted. Change serial port configu- ration or execute software reset in single byte instruction only to avoid unexpected device behavior. Table 14. Register Name Address Default SPI Control ...

Page 21

... AUXDAC2<9:8> 7 AUX2PIN 6 AUX2DIR AD9741/AD9743/AD9745/AD9746/AD9747 Description 0, operate SPI in 4-wire mode, SDIO pin operates as an input only 1, operate SPI in 3-wire mode, SDIO pin operates as a bidirectional I/O line 0, LSBFIRST off, SPI serial data mode is MSB to LSB 1, LSBFIRST on, SPI serial data mode is LSB to MSB 0, resume normal operation following software RESET 1, software RESET ...

Page 22

... RESET pin should follow. This insures the default state of all control register bits. In addition, once the RESET pin goes low, the SPI port can be activated, so CSB should be held high. For applications without a controller, the AD9741/AD9743/ AD9745/AD9746/AD9747 also support pin mode operation, which allows some functional options to be pin, selected with- out the use of the SPI port ...

Page 23

... Figure 32. DAC Clock VCM Circuit AD9741/AD9743/AD9745/AD9746/AD9747 It is important to use CVDD18 and CVSS for any clock bias circuit as noise that is coupled onto the clock from another power supply is multiplied by the DAC input signal and degrades performance. FULL-SCALE CURRENT GENERATION ...

Page 24

... AD9741/AD9743/AD9745/AD9746/AD9747 DAC TRANSFER FUNCTION Each DAC output of the AD9741/AD9743/AD9745/AD9746/ AD9747 drives complementary current outputs I I provides a near full-scale current output (I OUTP are high. For example, N DAC CODE = 2 − 1 where 8-/10-/12-/14-/16-bits (for AD9741/AD9743/AD9745/ AD9746/AD9747 respectively), and I OUTN The current output appearing at I and I ...

Page 25

... F S Figure 36. Transfer Function for Each Analog Operating Mode AUXILIARY DACS Two auxiliary DACs are provided on the AD9741/AD9743/ AD9745/AD9746/AD9747. A functional diagram is shown in Figure 37. The auxiliary DACs are current output devices with two output pins, AUXP and AUXN. The active pin can be programmed to either source or sink current ...

Page 26

... AD9741/AD9743/AD9745/AD9746/AD9747 30 24 AD9747 100 125 150 f (MHz) DAC Figure 41. DVDD18 Current vs 100 125 150 f (MHz) DAC Figure 42. CVDD18 Current vs. f Figure 43 shows the power consumption for each power supply domain as well as the total power consumption. Individual bars within each group display the power in full active mode (blue) vs ...

Page 27

... AD9746BCPZ −40°C to +85°C 1 AD9746BCPZRL −40°C to +85°C 1 AD9747BCPZ −40°C to +85°C 1 AD9747BCPZRL −40°C to +85°C 1 AD9741-EBZ 1 AD9743-EBZ 1 AD9745-EBZ 1 AD9746-EBZ 1 AD9747-EBZ RoHS Compliant Part. AD9741/AD9743/AD9745/AD9746/AD9747 0.60 0.42 0.24 54 0.50 9.75 BSC BSC SQ 0.50 37 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.30 0.08 0.20 REF 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 Figure 44. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ × ...

Page 28

... AD9741/AD9743/AD9745/AD9746/AD9747 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06569-0-5/07(0) Rev Page ...

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