CS3318-CQZ Cirrus Logic Inc, CS3318-CQZ Datasheet
CS3318-CQZ
Specifications of CS3318-CQZ
Available stocks
Related parts for CS3318-CQZ
CS3318-CQZ Summary of contents
Page 1
... The CS3318 implements configurable zero-crossing detection to provide glitch-free volume-level changes. The I²C/SPI control interface provides for easy system integration 128 CS3318 devices over a single 2- wire I²C or 3-wire SPI bus, allowing many channels of volume control with minimal system controller I/O re- quirements. Devices may be controlled on an individual ...
Page 2
... Zero-Crossing Modes ........................................................................................................ 22 5.7.2 Zero-Crossing Time-Out .................................................................................................... 22 5.8 System Serial Control Configuration ........................................................................................... 23 5.8.1 Serial Control within a Single-CS3318 System ................................................................. 23 5.8.2 Serial Control within a Multiple-CS3318 System ............................................................... 24 5.8.2.1 SPI Mode Serial Control Configuration .......................................................................................... 24 5.8.2.2 I²C Mode Control Configuration ..................................................................................................... 26 5.9 I²C/SPI Serial Control Formats .................................................................................................... 27 5.9.1 I²C Mode ............................................................................................................................ 27 5 ...
Page 3
... Individual Chip Address (Bits 7:1) ................................................................................... 41 7.20.2 Enable Next Device (Bit 0) .............................................................................................. 41 7.21 Chip ID - Address 1Ch ............................................................................................................... 41 7.21.1 Chip ID (Bits 7:4) ............................................................................................................. 41 7.21.2 Chip Revision (Bits 3:0) ................................................................................................... 41 8. PARAMETER DEFINITIONS .............................................................................................................. 42 9. PACKAGE DIMENSIONS .................................................................................................................. 43 10. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................ 43 11. ORDERING INFORMATION ............................................................................................................ 44 12. REVISION HISTORY ........................................................................................................................ 44 DS693F1 CS3318 3 ...
Page 4
... Figure 1.Control Port Timing - I²C Format.................................................................................................. 10 Figure 2.Control Port Timing - SPI Format................................................................................................. 11 Figure 3.Typical Connection Diagram........................................................................................................ 12 Figure 4.Detailed Block Diagram ............................................................................................................... 13 Figure 5.CS3318 Control Mapping Matrix.................................................................................................. 17 Figure 6.Volume & Muting Control Implementation ................................................................................... 18 Figure 7.Standard I²C Connections............................................................................................................ 23 Figure 8.Standard SPI Connections........................................................................................................... 23 Figure 9.SPI Serial Control Connections ................................................................................................... 24 Figure 10.Individual Device Address Configuration Process ..................................................................... 25 Figure 11.I² ...
Page 5
... REFI8 11 IN8 12 Pin Name # Pin Description IN1 1 IN2 42 IN3 39 IN4 32 Analog Inputs (Input) - The full-scale level is specified in the Analog Characteristics specification table. IN5 29 IN6 22 IN7 19 IN8 12 DS693F1 CS3318 CS3318 36 VA- VA+ 35 OUT4 34 REFO4 33 IN4 32 REFI4 31 REFI5 30 IN5 29 REFO5 28 OUT5 27 26 VA- VA ...
Page 6
... I²C Mode the chip-select signal for SPI format. ENOut 8 Enable Output (Output) - Enable output signal for multi-device serial control chain configuration. DGND 9 Digital Ground (Input) - Ground reference for the internal digital section Digital Power (Input) - Positive power for the internal digital section. 6 CS3318 DS693F1 ...
Page 7
... Digital VD 3.1 T -10 A (Note 1) Symbol Min Positive Analog VA+ -0.3 Negative Analog VA- -10.5 Digital VD -0.3 (Note (VA-) - 0.3 INA 0.3 IND stg CS3318 Nom Max Units 9.0 9.45 V -9.0 -7.6 V 3.3 3.5 V °C - +70 Max Units 10.5 V 0.3 V 3.63 V ± (VA 0.3 V °C ...
Page 8
... V FS (Note 4) (1 kHz) (Note OUT R LOAD Normal Operation I VA (Note Normal Operation Power Down (Note 5) PSRR ) - 1 kHz, Volume = 0 dB. p p-p RMS CS3318 Min Typ Max - 0.25 - ±0 ±0 0.00025 0.00063 121 127 - (VA-) + 1.35 - (VA+) - 1.35 - 1.8 3.6 - -120 ...
Page 9
... Logic 0 = DGND, Logic 1 = VD) Parameters MUTE Active Pulse Width 6. The MUTE active state (low/high) is set by the MutePolarity bit in the Device Configuration 1 register (see page 33). DS693F1 Symbol Min Typ Symbol Min Typ (Note CS3318 Max Units - - 0.4 V μA - ± Max Units - - ms 9 ...
Page 10
... Symbol f scl t irs t buf t hdst t low t high t sust (Note 7) t hdd t sud susp t ack t high t sud t ack hdd Figure 1. Control Port Timing - I²C Format CS3318 Min Max - 100 100 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 fd 4.7 - 300 1000 , of SCL ate d Sta ...
Page 11
... RESET CS CCLK MOSI DS693F1 = 20 pF) L Symbol f sck t srs t csh t css t scl t sch t dsu (Note (Note (Note srs t scl t sch t css dsu t dh Figure 2. Control Port Timing - SPI Format CS3318 Min Max Unit 0 6.0 MHz 100 - ns μs 1 100 ns - 100 ns t csh 11 ...
Page 12
... AD0/CS 3 RESET 4 DGND MUTE 2 REFI1 REFO1 41 REFI2 REFO2 40 REFI3 REFO3 31 REFI4 REFO4 30 REFI5 REFO5 21 REFI6 REFO6 20 REFI7 REFO7 11 REFI8 REFO8 µF 0.1 µF 0.1 µF Figure 3. Typical Connection Diagram CS3318 + +9V 10 µ - Audio Outputs Next CS3318 +3 0.1 µ +9V 10 µ -9V DS693F1 ...
Page 13
... Zero Crossing Detector +22 dB Zero Crossing Detector OUT +22 dB Zero Crossing Detector OUT +22 dB Zero Crossing Detector OUT +22 dB Figure 4. Detailed Block Diagram CS3318 R OUT 47 OUT1 REFO1 48 OUT2 44 43 REFO2 OUT3 37 REFO3 38 34 OUT4 REFO4 33 ENOut DGND R OUT OUT5 27 28 REFO5 24 OUT6 REFO6 23 ...
Page 14
... Volume changes may be configured to occur immediately signal zero-crossing. In the event that the signal does not cross zero, the CS3318 provides 8 selectable time-out periods in the range after which the volume level will be changed immediately. When the CS3318 receives more than one vol- ume change command before a zero-crossing or a time-out, the CS3318 is able to implement the previous volume change command immediately or discard it and act only on the most recent command ...
Page 15
... VA+, VA-, and VD connected to clean supplies. Power supply decoupling capacitors should be placed as near to the CS3318 as possible, with the low value ceramic capacitor being the nearest. Care should be taken to ensure that there is minimal resis- tance in the analog ground leads to the device to prevent any changes in the defined gain/attenuation set- tings ...
Page 16
... The desired register settings can be loaded while the PDN_ALL bit remains set. 4. Clear the PDN_ALL bit to initiate the power-up sequence. 5.3.2 Recommended Power-Down Sequence 1. Set the PDN_ALL bit to mute all channels and power-down all internal amplifiers desired, hold RESET low to bring the CS3318’s power consumption to an absolute minimum. 16 CS3318 DS693F1 ...
Page 17
... Master control allows the volume and mute state of multiple channels to be changed simultaneously with a single register write. The CS3318 provides three master controls, and each may be configured to affect any group of channels within a device. Refer to the “ ...
Page 18
... Volume & Muting Control Implementation Figure 6 below diagrams in detail the volume and muting control architecture of the CS3318 for an arbi- trary channel ‘N’. This diagram incorporates all volume and muting control concepts presented in sections included as a reference and will serve to corroborate the information presented in these sections. ...
Page 19
... ChN In this equation, EffVol ChN “N” as determined by the its constituent volume settings within the CS3318. The effective volume is limited to the range of + -96 dB; see “Volume Limits” on page 20. Individual is the individual channel volume setting set by the channel’s individual volume con- ChN trol register and ¼ ...
Page 20
... Volume Limits The analog section of the CS3318 is designed to accommodate gain and attenuation over the range of + -96 dB. Values outside this range may, however, be written to the CS3318’s internal registers. As shown in Figure 6 on page summed before being limited to the range allowed by the CS3318’s analog section. This architecture has the benefit of allowing both individual and master volume control input beyond the analog range of the CS3318 ...
Page 21
... Hardware Mute Control The CS3318 implements a hardware MUTE input pin to allow the user to control the mute state of all chan- nels with an external level-active signal. By default, the MUTE input is configured for active low operation, and all channels will be held in a mute state whenever this input is low. ...
Page 22
... Zero-crossing detection and time-out is implemented independently for each channel. 5.7.1 Zero-Crossing Modes The zero-crossing mode for all channels within the CS3318 are configured via the ZCMode[1:0] bits in the Device Config 2 register. By default, zero-crossing mode 1 is selected. The zero-crossing modes are de- tailed in Table 2 ...
Page 23
... In a single CS3318 system, no special attention must be given to the serial control port operation of the CS3318. The standard serial control signals (SDA and SCL for I²C Mode, or MOSI, CCLK, and CS for SPI Mode) should be connected to the system controller, and the ENOut signal is not used (see Figures 7 and 8) ...
Page 24
... For instance, a system containing 8 CS3318’s may configure the Group 1 ad- dress of the first set of 4 CS3318’s to 10h, the Group 1 address of the second set of 4 CS3318’s to 20h, and the Group 2 address of all 8 CS3318’s to A0h. In this manner, a serial control data write to address ...
Page 25
... RESET pin), the Individual device address register must be written (using the CS3318’s default device address) with a unique device address, and the Enable bit must be set to take the next device in the serial control chain out of reset. This process may be repeated until all devices in the serial control chain have been assigned a new Individual device address ...
Page 26
... I²C Mode Control Configuration Up to 128 CS3318’s may be connected to a common I²C serial control bus. This shared serial bus is used to assign a unique device address to each device on the bus such that they may be independently ad- dressed. To implement this method of device address configuration, the devices must be connected as ...
Page 27
... All other transitions of SDA occur while the clock is low. The first byte sent to the CS3318 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). To communicate with a CS3318, the chip address field should match either the Individual, Group 1, or Group 2 device address as set by their respective control port registers ...
Page 28
... SPI Mode In SPI Mode the CS3318 chip-select signal, CCLK, is the control port bit clock (input into the CS3318 from the microcontroller), and MOSI is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The default chip address in SPI Mode is 1000000b. ...
Page 29
... CS3318 REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr Function 7 01h Ch. 1 Volume Vol7 page 31 1 02h Ch. 2 Volume Vol7 page 31 1 03h Ch. 3 Volume Vol7 page 31 1 04h Ch. 4 Volume Vol7 page 31 1 05h Ch. 5 Volume ...
Page 30
... M3_Ch5M M3_Vol6 M3_Vol5 M3_Vol4 Reserved Reserved Reserved G2_Addr5 G2_Addr4 G2_Addr3 G1_Addr5 G1_Addr4 G1_Addr3 Ind_Addr3 ID2 ID1 ID0 CS3318 M1_Ch4M M1_Ch3M M1_Ch2M M1_Ch1M M1_Vol3 M1_Vol2 M1_Vol1 Reserved Reserved M1_Mute M2_Ch4M M2_Ch3M M2_Ch2M M2_Ch1M M2_Vol3 M2_Vol2 M2_Vol1 Reserved Reserved M2_Mute M3_Ch4M M3_Ch3M M3_Ch2M M3_Ch1M ...
Page 31
... In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB resolution volume setting down to ½ dB resolution. It should be noted that input values outside the CS3318’s analog range of + -96 dB are valid, however, the volume of each channel will be limited to the CS3318’s analog range (see its” ...
Page 32
... ZCMode[1:0] and TimeOut[2:0] bits in the Device Config 2 register (see “Device Configuration 2 - Address 0Ch” on page It should be noted that input values outside the CS3318’s analog range of + -96 dB are valid; however, the volume of each channel will be limited to the CS3318’s analog range (see its” ...
Page 33
... This bit controls the active level of the MUTE input pin. When set, the mute condition is active when the MUTE pin is high. When cleared, the mute condition is active when the MUTE pin is low. DS693F1 MuteCh5 MuteCh4 for more information about the muting behavior of the CS3318 MutePolarity Ch8=7 CS3318 2 1 ...
Page 34
... Channel 2 register settings are ignored Table 7. Channel B = Channel A Settings TimeOut2 TimeOut1 for more information. Zero-Crossing TimeOut[2:0] Time-Out Period 000 001 010 011 100 101 110 111 Table 8. Zero-Crossing Time-Out Settings CS3318 2 1 TimeOut0 ZCMode1 ZCMode0 Table 9. Refer to the “Zero-Crossing DS693F1 0 ...
Page 35
... The control registers remain accessible, and their contents are retained while the device is in power-down. DS693F1 for more information. Zero-Crossing Mode Table 9. Zero-Crossing Mode Settings PDN5 PDN4 Reserved Reserved CS3318 Table 9. Refer to the “Zero-Cross PDN3 PDN2 PDN1 Reserved Reserved PDN_ALL ...
Page 36
... In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB resolution volume setting down to ½ dB resolution. It should be noted that input values outside the CS3318’s analog range of + -96 dB are valid, however, the volume of each channel will be limited to the CS3318’s analog range (see its” ...
Page 37
... The value of the Master 2 volume control register is mapped to the desired 0.5 dB step Master 2 vol- ume setting by the following equation: Register Value DS693F1 Reserved Reserved for more information about the muting behavior of the CS3318. for an example of volume settings using the ¼ dB control M2_Ch5M M2_Ch4M 5 4 ...
Page 38
... In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB resolution volume setting down to ½ dB resolution. It should be noted that input values outside the CS3318’s analog range of + -96 dB are valid; however, the volume of each channel will be limited to the CS3318’s analog range (see its” ...
Page 39
... In the equation above, “Desired Volume Setting in dB” is determined by rounding the desired ¼ dB resolution volume setting down to ½ dB resolution. It should be noted that input values outside the CS3318’s analog range of + -96 dB are valid, however, the volume of each channel will be limited to the CS3318’s analog range (see its” ...
Page 40
... G2_Addr3 G2_Addr2 Table 4 on page 27. and “I²C/SPI Serial Control Formats” on page G1_Addr3 G1_Addr2 Table 4 on page 27. and “I²C/SPI Serial Control Formats” on page 27 CS3318 G2_Addr1 G2_Addr0 EnG2Addr “System Serial Con- for more information G1_Addr1 G1_Addr0 EnG1Addr “System Serial Con- for more information ...
Page 41
... These bits set the individual chip address, and may be modified at any time. See trol Configuration” on page 23 7.20.2 Enable Next Device (Bit 0) Default = 0 Function: When set, the CS3318’s enable output pin (ENOut) will be driven high. When cleared, the CS3318’s enable output pin (ENOut) will be driven low. 7.21 Chip ID - Address 1Ch 7 ...
Page 42
... Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 42 CS3318 DS693F1 ...
Page 43
... Symbol θ 48-LQFP JA θ JC CS3318 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7 ...
Page 44
... Changes measurement condition for the Analog Characteristics L Analog Characteristics Analog Characteristics Analog Characteristics Analog Characteristics page www.cirrus.com. CS3318 Temp Range Container Order # Tray CS3318-CQZ Tape & Reel CS3318-CQZR - - CDB3318 table on page 8. table on page 8 table on page 8. table on page 8. Analog Characteristics table on page ...