AD5449 Analog Devices, AD5449 Datasheet
AD5449
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AD5449 Summary of contents
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... DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with 0s, and the DAC outputs are at zero scale. The AD5429/AD5439/AD5449 DACs are available in 16-lead TSSOP packages. The EVAL-AD5415/AD5449SDZ evaluation board is available for evaluating DAC performance. For more information, see the UG-297 evaluation board user guide ...
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... Changes to Table 5.......................................................................... 15 Changes to Table 6.......................................................................... 16 Changes to Single-Supply Applications Section......................... 17 Changes to Divider or Programmable Gain Element Section .... 18 Changes to Table 7 Through Table 10 ......................................... 20 Added ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface Section ........................................................................ 23 Change to PCB Layout and Power Supply Decoupling Section .......................................... 25 Changes to Power Supplies for the Evaluation Board Section.... 25 Changes to Table 13 ...
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... MHz 80 120 nV-sec Rev Page AD5429/AD5439/AD5449 to T MIN MAX Conditions Guaranteed monotonic Guaranteed monotonic Guaranteed monotonic Data = 0x0000 25° OUT Data = 0x0000 OUT Input resistance temperature coefficient = −50 ppm/°C Typical = 25°C, maximum = 125° ...
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... V p-p, all 1s loaded kHz REF Clock = 10 MHz 3.5 V REF AD5449, 65k codes 3.5 V REF AD5449, 65k codes 3.5 V REF AD5449, 65k codes 3.5 V REF Clock = 10 MHz Clock = 25 MHz T = 25°C, logic inputs = −40°C to +125°C, logic inputs = ∆ ...
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... Consists of cycle time, SYNC high time, data setup, and output voltage settling time DB0 t 9 Figure 2. Standalone Mode Timing Diagram Rev Page AD5429/AD5439/AD5449 + V )/ unless otherwise noted. MIN MAX 2 5.5 V, ...
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... AD5429/AD5439/AD5449 SCLK t 4 SYNC t 5 DB15 SDIN (N) SDO NOTES 1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON THE FALLING EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED. ...
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... Only one absolute maximum rating may be −0 applied at any one time. ±10 mA −0 0 ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 150°C/W 300°C 235°C Rev Page AD5429/AD5439/AD5449 ...
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... OUT OUT AD5429 AD5439 REF REF AD5449 GND TOP VIEW LDAC 6 11 CLR (Not to Scale) SCLK 7 10 SYNC SDIN 8 9 SDO CONNECT Figure 6. Pin Configuration Rev Page ...
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... Rev Page AD5429/AD5439/AD5449 T = 25° 10V REF 100 150 200 CODE Figure 10. DNL vs. Code (8-Bit DAC 25° 10V REF ...
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... AD5429/AD5439/AD5449 0.6 0.5 0.4 MAX INL 0.3 0.2 0.1 0 MIN INL –0.1 –0.2 –0 REFERENCE VOLTAGE Figure 13. INL vs. Reference Voltage –0. 25° –0.45 –0.50 –0.55 –0.60 MIN DNL –0.65 –0. REFERENCE VOLTAGE Figure 14. DNL vs. Reference Voltage ...
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... COMP AMP = AD8038 –0.010 1M 10M 100M –1.68 –1.69 –1.70 –1.71 –1.72 –1.73 –1.74 –1.75 –1.76 –1.77 1M 10M 100M Rev Page AD5429/AD5439/AD5449 = 25° ±2V, AD8038 C 1.47pF REF ±2V, AD8038 C 1pF REF ±0.15V, AD8038 C 1pF REF ± ...
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... AD5429/AD5439/AD5449 25° AMP = AD8038 0 –20 –40 FULL SCALE –60 ZERO SCALE –80 –100 –120 1 100 1k 10k 10 FREQUENCY (Hz) Figure 25. Power Supply Rejection Ratio vs. Frequency – 25° 3.5V p-p –65 REF –70 –75 –80 –85 – 100 1k FREQUENCY (Hz) Figure 26 ...
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... Figure 35. Wideband IMD, f 300 T = 25° AMP = AD8038 250 65k CODES 200 150 100 120 130 140 150 Rev Page AD5429/AD5439/AD5449 AMP = AD8038 65k CODES 100 105 FREQUENCY (kHz kHz, 100 kHz, Clock = 10 MHz OUT ...
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... AD5429/AD5439/AD5449 TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function measured after adjusting for zero and full scale and is typically expressed in LSBs percentage of the full-scale reading. Differential Nonlinearity The difference in the measured change and the ideal 1 LSB change between two adjacent codes ...
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... The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit, dual- channel, current output DACs consisting of a standard inverting R-2R ladder configuration. Figure 37 shows a simplified diagram for a single channel of the AD5449. The feedback resistor, R has a value of R. The value typically 10 kΩ (with a minimum of 8 kΩ and a maximum of 12 kΩ). If I ...
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... D is the fractional representation of the digital word loaded to the DAC 255 (AD5429 1023 (AD5439 4095 (AD5449 the number of bits. Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation with the AD5429. ...
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... GND NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED HIGH SPEED AMPLIFIER. Figure 41. Positive Voltage Output with Minimum Components Rev Page AD5429/AD5439/AD5449 is limited to low voltages because the switches IN must not go negative OUT ...
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... AD5429/AD5439/AD5449 ADDING GAIN In applications in which the output voltage must be greater than V , gain can be added with an additional external amplifier can be achieved in a single stage. Consider the effect of temper- ature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor causes mismatches in the temperature coefficients, resulting in larger gain temper- ature coefficient errors ...
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... Noise (μV p-p) B 0.1 0.5 2 0.4 0.05 1 0.001 2.3 0.1 0.5 Slew Rate (V/μs) VOS (Max) (μV) 180 1500 120 1000 425 3000 1300 10,000 Rev Page AD5429/AD5439/AD5449 Output Noise (μV p-p) Package 20 SOIC-8 20 TSOT-23, SC70 10 SOIC-8 10 TSOT-23, SC70 6 SOIC-8 6 TSOT-23, SC70 10 SOIC-8 10 TSOT-23, SC70 3.5 SOIC-8 8 SOIC-8 ...
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... DB3 DATA BITS Figure 45. AD5439 10-Bit Input Shift Register Contents C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DATA BITS Figure 46. AD5449 12-Bit Input Shift Register Contents 1 SDO2 SDO1 DSY HCLR SCLK X X Figure 47. Control Register Loading Sequence Rev Page SDO1 ...
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... Load and update B Initiate readback B Load input register A and B Update DAC outputs A and B Load input registers N/A Disable daisy-chain N/A Clock data to shift register on rising edge N/A Clear DAC output to zero scale N/A Clear DAC output to midscale N/A Control word N/A Reserved N/A No operation Rev Page AD5429/AD5439/AD5449 ...
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... DSP processors. The communication channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5429/AD5439/ AD5449 require a 16-bit word, with the default being data valid on the falling edge of SCLK; however, this is changeable using the control bits in the data-word. ...
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... PINS OMITTED FOR CLARITY. Figure 53. MCH68HC11/68L11-to-AD5429/AD5439/AD5449 Interface The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5429/AD5439/AD5449, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle ...
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... In any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5429/AD5439/AD5449 is mounted should be designed so that the analog and digital sections are separate and confined to certain areas of the board. If the DAC system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only ...
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... Parallel RU-28 ±2 Serial RU-16 ±2 Parallel RU-38 Rev Page AD5429/AD5439/AD5449 Features 10 MHz BW pulse width 10 MHz BW, 50 MHz serial 10 MHz BW pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW pulse width ...
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... Model Resolution AD5429YRU 8 AD5429YRU-REEL 8 AD5429YRU-REEL7 8 AD5429YRUZ 8 AD5429YRUZ-REEL 8 AD5429YRUZ-REEL7 8 AD5439YRU 10 AD5439YRU-REEL 10 AD5439YRU-REEL7 10 AD5439YRUZ 10 AD5439YRUZ-REEL 10 AD5439YRUZ-REEL7 10 AD5449YRU 12 AD5449YRU-REEL 12 AD5449YRU-REEL7 12 AD5449YRUZ 12 AD5449YRUZ-REEL 12 AD5449YRUZ-REEL7 12 EVAL-AD5449SDZ RoHS Compliant Part. 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8° 0.30 0° 0.65 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 56. 16-Lead Thin Shrink Small Outline Package [TSSOP] ...
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... NOTES AD5429/AD5439/AD5449 Rev Page ...
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... AD5429/AD5439/AD5449 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04464-0-6/11(D) Rev Page ...