AD5338

Manufacturer Part NumberAD5338
Description2.5 V to 5.5 V, 250 µA, 2-Wire Interface, Dual Voltage Output, 10-Bit DACs
ManufacturerAnalog Devices
AD5338 datasheet
 


Specifications of AD5338

Resolution (bits)10bitDac Update Rate14.8kSPS
Dac Settling Time7µsMax Pos Supply (v)+5.5V
Single-supplyYesDac TypeVoltage Out
Dac Input FormatI2C/Ser 2-wire  
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FEATURES
AD5337
2 buffered 8-bit DACs in 8-lead MSOP
AD5338, AD5338-1
2 buffered 10-bit DACs in 8-lead MSOP
AD5339
2 buffered 12-bit DACs in 8-lead MSOP
Low power operation: 250 μA @ 3 V, 300 μA @ 5 V
2
2-wire (I
C-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
3 power-down modes
Double-buffered input logic
Output range: 0 V to V
REF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
SCL
INTERFACE
SDA
LOGIC
A0
POWER-ON
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2.5 V to 5.5 V, 250 μA, 2-Wire Interface,
Dual Voltage Output, 8-/10-/12-Bit DACs
GENERAL DESCRIPTION
The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit
buffered voltage output DACs, respectively. Each part is housed
in an 8-lead MSOP package and operates from a single 2.5 V to
5.5 V supply, consuming 250 μA at 3 V. On-chip output amplifiers
allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2-
wire serial interface operates at clock rates up to 400 kHz. This
interface is SMBus compatible at V
can be placed on the same bus.
The references for the two DACs are derived from one reference
pin. The outputs of all DACs can be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit to ensure that the DAC outputs power up
to 0 V and remain there until a valid write to the device takes
place. A software clear function resets all input and DAC
registers to 0 V. A power-down feature reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is typically 1.5 mW at 5 V and
0.75 mW at 3 V, reducing to 1 μW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
V
REFIN
DD
LDAC
INPUT
DAC
STRING
REGISTER
REGISTER
DAC A
INPUT
DAC
STRING
REGISTER
REGISTER
DAC B
AD5337/AD5338/AD5339
RESET
GND
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD5337/AD5338/AD5339
< 3.6 V. Multiple devices
DD
V
A
BUFFER
OUT
BUFFER
V
B
OUT
POWER-DOWN
LOGIC
www.analog.com
©2003–2007 Analog Devices, Inc. All rights reserved.

AD5338 Summary of contents

  • Page 1

    ... V to 5.5 V, 250 μA, 2-Wire Interface, Dual Voltage Output, 8-/10-/12-Bit DACs GENERAL DESCRIPTION The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit buffered voltage output DACs, respectively. Each part is housed in an 8-lead MSOP package and operates from a single 2 5.5 V supply, consuming 250 μ On-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 V/μ ...

  • Page 2

    ... Product as a Digitally Programmable Window Detector ..... 21 Coarse and Fine Adjustment Capabilities............................... 21 Power Supply Decoupling ......................................................... 21 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 10/04—Rev Rev. A Updated Format..................................................................Universal Added AD5338-1................................................................Universal Changes to Specifications.................................................................4 Updated Outline Dimensions....................................................... 24 Changes to Ordering Guide .......................................................... 24 11/03—Rev. 0: Initial Version Rev Page ...

  • Page 3

    ... V − V − 0.001 0.001 0.5 0 2.5 2 Rev Page AD5337/AD5338/AD5339 unless otherwise noted. MIN MAX 1 Max Unit Conditions/Comments Bits ±0.5 LSB ±0.25 LSB Guaranteed monotonic by design over all codes Bits ±2 LSB ±0.50 LSB Guaranteed monotonic by ...

  • Page 4

    ... See the Terminology section for explanations of the specific parameters specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-1 (Code 28 to Code 995), AD5339 (Code 115 to Code 3981). 5 Guaranteed by design and characterization; not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative ...

  • Page 5

    ... V/μs 12 nV-s 1 nV-s 1 nV-s 3 nV-s 200 kHz −70 dB Rev Page AD5337/AD5338/AD5339 unless otherwise noted. MAX Conditions/Comments REF DD 1/4 scale to 3/4 scale change (0x40 to 0xC0) 1/4 scale to 3/4 scale change (0x100 to 0x300) 1/4 scale to 3/4 scale change (0x400 to 0xC00) 1 LSB change around major carry ± 0.1 V p-p ...

  • Page 6

    ... AD5337/AD5338/AD5339 TIMING CHARACTERISTICS 5.5 V. All specifications T DD Table 3. Limit MIN MAX Parameter A Version and B Version f 400 SCL 100 300 250 11 0 300 0 400 master device must provide a hold time of at least 300 ns for the SDA signal (referred to V ...

  • Page 7

    ... Exposure to absolute + 0 maximum rating conditions for extended periods may affect + 0 device reliability Transient currents 100 mA do not cause SCR latch-up ESD CAUTION ) θ Rev Page AD5337/AD5338/AD5339 ...

  • Page 8

    ... Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift register. Clock rates 400 kbps can be accommodated in the 2-wire interface Address Input. Sets the least significant bit of the 7-bit slave address AD5337/ DD AD5338 SCL 2 7 OUT AD5339 V B SDA ...

  • Page 9

    ... CODE Figure 4. AD5337 Typical INL Plot 25° –1 –2 –3 0 200 400 600 CODE Figure 5. AD5338 Typical INL Plot 25° –4 –8 –12 0 500 1000 1500 2000 2500 CODE Figure 6. AD5339 Typical INL Plot ...

  • Page 10

    ... AD5337/AD5338/AD5339 0. 25° 0.25 MAX DNL MAX INL 0 MIN DNL –0.25 MIN INL –0.50 0 0.5 1.0 1.5 2.0 2.5 3.0 V (V) REF Figure 10. AD5337 INL and DNL Error vs REF 0.3 0.2 0.1 MAX DNL 0 –0.1 –0.2 MIN INL –0.3 –0.4 –0.5 – TEMPERATURE (°C) Figure 11. AD5337 INL and DNL Error vs. Temperature 1 ...

  • Page 11

    ... CH1 CH2 4.5 5.0 5.5 CH1 –40°C CH2 +105°C 4.5 5.0 5.5 CH1 CH2 3.5 4.0 4.5 5.0 Rev Page AD5337/AD5338/AD5339 T = 25° REF V A OUT SCL CH1 1V, CH2 5V, TIME BASE = 1µs/DIV Figure 19. Midscale Settling (¼ to ¾ Scale Code Change 25° ...

  • Page 12

    ... AD5337/AD5338/AD5339 150 200 250 I (µA) DD Figure 22. I Histogram with and 2.50 2.49 2.48 2.47 1µs/DIV Figure 23. AD5339 Major Code Transition Glitch Energy 10 0 –10 –20 –30 –40 –50 –60 10 100 1k 10k FREQUENCY (Hz) Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response –0.01 – ...

  • Page 13

    ... The difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonic distortion present in the DAC output measured in dB. Rev Page AD5337/AD5338/AD5339 ...

  • Page 14

    ... AD5337/AD5338/AD5339 OUTPUT IDEAL VOLTAGE ACTUAL NEGATIVE OFFSET DAC CODE ERROR DEADBAND CODES AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR Figure 27. Transfer Function with Negative Offset GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE POSITIVE OFFSET Rev Page GAIN ERROR PLUS OFFSET ERROR ...

  • Page 15

    ... OUT POWER-ON RESET OUTPUT BUFFER AMPLIFIER The AD5337/AD5338/AD5339 power defined state via a power-on reset function. The power-on state is normal operation, with output voltage set Both input and DAC registers are filled with zeros until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering on ...

  • Page 16

    ... A0 pin. The facility of making hardwired changes to A0 allows the use of one or two of these devices on one bus. The AD5338-1 has a unique 7-bit slave address. The six MSBs are 010001, and the LSB is determined by the state of the A0 pin. Using a combination of AD5338 and AD5338-1 allows the user to accommodate four of these dual 10-bit devices (eight channels) on the same bus ...

  • Page 17

    ... CLR , which is 1. WRITE OPERATION When writing to the AD5337/AD5338/AD5339 DACs, the user must begin with an address byte ( 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low ...

  • Page 18

    ... AD5337/AD5338/AD5339 READ OPERATION When reading data back from the AD5337/AD5338/AD5339 DACs, the user begins with an address byte ( 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte is usually followed by the pointer byte, which is also acknowledged by the DAC. Then, the master initiates another start condition (repeated start) and the address is resent with ...

  • Page 19

    ... LDAC was brought low, thereby removing unnecessary digital crosstalk. POWER-DOWN MODES The AD5337/AD5338/AD5339 have very low power consumption, typically dissipating 0.75 mW with supply and 1.5 mW with supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bit 15 and Bit 14 (PD1 and PD0) of the data byte ...

  • Page 20

    ... DD solution is to connect the reference input to V supply can be inaccurate and noisy, the AD5337/AD5338/ AD5339 can be powered from a reference voltage, for example, using reference such as the REF195, which provides a steady output supply voltage. With no load on the DACs, the REF195 is required to supply 600 μ ...

  • Page 21

    ... The printed circuit board on which the AD5337/AD5338/AD5339 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5337/AD5338/AD5339 are in a system where multiple devices require an AGND-to- DGND connection, the connection should be made at one 1kΩ ...

  • Page 22

    ... AD5311 10 1 AD5321 12 1 Dual AD5302 8 2 AD5312 10 2 AD5322 12 2 AD5303 8 2 AD5313 10 2 AD5323 12 2 AD5337 8 2 AD5338 10 2 AD5338 AD5339 12 2 Quad AD5304 8 4 AD5314 10 4 AD5324 12 4 AD5305 8 4 AD5315 10 4 AD5325 12 4 AD5306 8 4 AD5316 10 4 ...

  • Page 23

    ... Rev Page AD5337/AD5338/AD5339 HBEN CLR Package No. of Pins * TSSOP 20 * TSSOP 20 * TSSOP TSSOP 20 * TSSOP 20 * TSSOP 24 * TSSOP TSSOP 20 * TSSOP TSSOP 24 * TSSOP 28 TSSOP 28 * TSSOP, LFCSP 38 TSSOP, LFCSP ...

  • Page 24

    ... AD5338ARMZ-1 1 −40°C to +105°C 1 AD5338ARMZ-1REEL7 −40°C to +105°C AD5338BRM −40°C to +105°C AD5338BRM-REEL −40°C to +105°C AD5338BRM-REEL7 −40°C to +105°C 1 AD5338BRMZ −40°C to +105°C 1 AD5338BRMZ-1 −40°C to +105°C 1 AD5338BRMZ-1REEL7 −40°C to +105°C AD5339ARM − ...

  • Page 25

    ... NOTES AD5337/AD5338/AD5339 Rev Page ...

  • Page 26

    ... AD5337/AD5338/AD5339 NOTES Rev Page ...

  • Page 27

    ... NOTES AD5337/AD5338/AD5339 Rev Page ...

  • Page 28

    ... AD5337/AD5338/AD5339 NOTES Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips © ...