AD5339

Manufacturer Part NumberAD5339
Description2.5 V to 5.5 V, 250 µA, 2-Wire Interface, Dual Voltage Output,12-Bit DACs
ManufacturerAnalog Devices
AD5339 datasheet
 

Specifications of AD5339

Resolution (bits)12bitDac Update Rate14.8kSPS
Dac Settling Time8µsMax Pos Supply (v)+5.5V
Single-supplyYesDac TypeVoltage Out
Dac Input FormatI2C/Ser 2-wire  
1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
25
26
27
28
Page 19/28

Download datasheet (587Kb)Embed
PrevNext
DOUBLE-BUFFERED INTERFACE
The AD5337/AD5338/AD5339 DACs have a double-buffered
interface consisting of two banks of registers—an input register
and a DAC register per channel. The input register is directly
connected to the input shift register, and the digital code is
transferred to the relevant input register upon completion of a
valid write sequence. The DAC register contains the digital code
used by the resistor string.
Access to the DAC register is controlled by the LDAC bit.
When the LDAC bit is set high, the DAC register is latched
and therefore, the input register can change state without
affecting the DAC register. This is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually; by setting the LDAC
bit low when writing to the remaining DAC input register, all
outputs update simultaneously.
These parts contain an extra feature whereby the DAC register
is only updated if its input register has been updated since the
last time that LDAC was brought low, thereby removing
unnecessary digital crosstalk.
POWER-DOWN MODES
The AD5337/AD5338/AD5339 have very low power consumption,
typically dissipating 0.75 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 15 and Bit 14
(PD1 and PD0) of the data byte. Table 8 shows how the state of
the bits corresponds to the mode of operation of the DAC.
Table 8. PD1/PD0 Operating Modes
PD1
PD0
Operating Mode
0
0
Normal operation
0
1
Power-down (1 kΩ load to GND)
1
0
Power-down (100 kΩ load to GND)
1
1
Power-down (three-state output)
AD5337/AD5338/AD5339
When both bits are 0, the DAC works with its normal power
consumption of 300 μA at 5 V. However, for the three power-
down modes, the supply current falls to 200 nA at 5 V (80 nA
at 3 V). Not only does the supply current drop, but the output
stage is also internally switched from the output of the amplifier
to a resistor network of known values. This is advantageous in
that the output impedance of the part is known while the part is
in power-down mode, which provides a defined input condition
for whatever is connected to the output of the DAC amplifier.
There are three options. The output can be connected internally
to GND through a 1 kΩ resistor, a 100 kΩ resistor, or can be left
open-circuited (three-state). Resistor tolerance = ±20%. The
output stage is illustrated in Figure 35.
RESISTOR
AMPLIFIER
STRING DAC
POWER-DOWN
CIRCUITRY
Figure 35. Output Stage During Power-Down
The bias generator, output amplifiers, resistor string, and all
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
registers remain unchanged when power-down mode is activated.
The time to exit power-down is typically 2.5 μs for V
and 5 μs when V
= 3 V. This is the time from the rising edge
DD
of the eighth SCL pulse to the time when the output voltage
deviates from its power-down voltage (see Figure 21 for a plot).
Rev. C | Page 19 of 28
V
OUT
RESISTOR
NETWORK
= 5 V
DD