AD5333

Manufacturer Part NumberAD5333
Description
ManufacturerAnalog Devices
AD5333 datasheet
 


Specifications of AD5333

Resolution (bits)10bitDac Update Rate143kSPS
Dac Settling Time7µsMax Pos Supply (v)+5.5V
Single-supplyYesDac TypeVoltage Out
Dac Input FormatPar  
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FEATURES
AD5332: Dual 8-Bit DAC in 20-Lead TSSOP
AD5333: Dual 10-Bit DAC in 24-Lead TSSOP
AD5342: Dual 12-Bit DAC in 28-Lead TSSOP
AD5343: Dual 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 230 A @ 3 V, 300 A @ 5 V
via PD Pin
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–V
or 0–2 V
REF
REF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
DB
.
7
.
.
DB
0
INTER-
FACE
LOGIC
CS
WR
A0
CLR
LDAC
.
*Protected by U.S. Patent Number 5,969,657
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
2.5 V to 5.5 V, 230 A, Parallel Interface
Dual Voltage-Output 8-/10-/12-Bit DACs
AD5332/AD5333/AD5342/AD5343*
GENERAL DESCRIPTION
The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 230 µA at 3 V, and feature a power-down pin, PD
that further reduces the current to 80 nA. These devices incor-
porate an on-chip output buffer that can drive the output to
both supply rails, while the AD5333 and AD5342 allow a choice
of buffered or unbuffered reference input.
The AD5332/AD5333/AD5342/AD5343 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5333 and AD5342 allows the output
range to be set at 0 V to V
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5332/AD5333/AD5342/AD5343 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5332 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
V
A
REF
POWER-ON
RESET
DAC
INPUT
8-BIT
REGISTER
REGISTER
DAC
DAC
INPUT
8-BIT
REGISTER
REGISTER
DAC
RESET
V
B
REF
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
or 0 V to 2 × V
.
REF
REF
V
DD
AD5332
V
A
BUFFER
OUT
BUFFER
V
B
OUT
POWER-DOWN
LOGIC
PD
GND
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000

AD5333 Summary of contents

  • Page 1

    ... The AD5332/AD5333/AD5342/AD5343 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin on the AD5333 and AD5342 allows the output range to be set Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin ...

  • Page 2

    ... See Terminology section. 2 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. 3 Linearity is tested using a reduced code range: AD5332 (Code 8 to 255); AD5333 (Code 28 to 1023); AD5342/AD5343 (Code 115 to 4095 specifications tested with outputs unloaded. 5 This corresponds to x codes ...

  • Page 3

    ... CLR A0 1 SYNCHRONOUS LDAC UPDATE MODE 2 ASYNCHRONOUS LDAC UPDATE MODE Figure 1. Parallel Interface Timing Diagram –3– AD5332/AD5333/AD5342/AD5343 to T MIN Conditions/Comments See Figure 20 REF 1/4 Scale to 3/4 Scale Change ( 1/4 Scale to 3/4 Scale Change (100 H to 300 H) 1/4 Scale to 3/4 Scale Change (400 H to C00 H) ...

  • Page 4

    ... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5332/AD5333/AD5342/AD5343 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. θ ...

  • Page 5

    ... V Power Supply Pin. These parts can operate from 2 5.5 V and the supply should be decoupled with capacitor in parallel with a 0.1 F capacitor to GND. 13–20 DB –DB Eight Parallel Data Inputs REV. 0 AD5332/AD5333/AD5342/AD5343 REF DD AD5332 8-BIT V BUFFER OUT DAC 8-BIT ...

  • Page 6

    ... Parallel Data Inputs REF DD AD5333 10-BIT BUFFER V OUT DAC 10-BIT BUFFER V OUT DAC POWER-DOWN LOGIC GND REF AD5333 PIN FUNCTION DESCRIPTIONS is the MSB of these 10 bits. 9 –6– AD5333 PIN CONFIGURATION GAIN BUF REF ...

  • Page 7

    ... Power-Down Pin. This active low control pin puts all DACs into power-down mode Power Supply Pin. These parts can operate from 2 5.5 V and the supply should be decoupled with capacitor in parallel with a 0.1 F capacitor to GND. 17–28 DB –DB 12 Parallel Data Inputs REV. 0 AD5332/AD5333/AD5342/AD5343 REF DD AD5342 12-BIT BUFFER V A OUT DAC ...

  • Page 8

    ... AD5332/AD5333/AD5342/AD5343 AD5343 FUNCTIONAL BLOCK DIAGRAM POWER-ON RESET HIGH BYTE REGISTER LOW BYTE DB REGISTER 0 HBEN INTER- HIGH BYTE CS FACE REGISTER LOGIC WR LOW BYTE REGISTER A0 RESET CLR LDAC Pin No. Mnemonic Function 1 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register ...

  • Page 9

    ... DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. This is illus- trated in Figure 2. ACTUAL OUTPUT VOLTAGE IDEAL DAC CODE Figure 2. Gain Error REV. 0 AD5332/AD5333/AD5342/AD5343 OUTPUT VOLTAGE POSITIVE OFFSET Figure 3. Positive Offset Error and Gain Error OUTPUT VOLTAGE NEGATIVE OFFSET ...

  • Page 10

    ... AD5332/AD5333/AD5342/AD5343 OFFSET ERROR DRIFT This is a measure of the change in Offset Error with changes in temperature expressed in (ppm of full-scale range)/°C. GAIN ERROR DRIFT This is a measure of the change in Gain Error with changes in tem- perature expressed in (ppm of full-scale range)/°C. POWER-SUPPLY REJECTION RATIO (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage ...

  • Page 11

    ... CODE Figure 6. AD5333 Typical INL Plot 0 0.4 0.2 0 –0.2 –0.4 –0.6 0 200 400 600 800 1000 CODE Figure 9. AD5333 Typical DNL Plot 1. 0.75 REF 0.50 MAX DNL MAX INL 0.25 0 –0.25 MIN INL MIN DNL –0.50 –0.75 –1.00 – ...

  • Page 12

    ... AD5332/AD5333/AD5342/AD5343 0 0 REF 0 GAIN ERROR –0.1 –0.2 –0.3 –0.4 OFFSET ERROR –0.5 –0 – Volts DD Figure 14. Offset Error and Gain Error vs 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V – Figure 17. Supply Current vs. Supply ...

  • Page 13

    ... They operate from single supplies of 2 5.5 V and the output buffer amplifiers offer rail-to-rail output swing. The AD5333 and AD5342 have reference inputs that may be buff- ered to draw virtually no current from the reference source. Their output voltage range may be configured ...

  • Page 14

    ... REF OUT If a gain selected (GAIN = 0), the output range is 0.001 REF If a gain selected (GAIN = 1), on the AD5333 and AD5342 the output range is 0.001 REF The output amplifier is capable of driving a load of 2 kΩ to GND parallel with 500 pF to GND source and sink capabilities of the output amplifi ...

  • Page 15

    ... X = don’t care. REV. 0 AD5332/AD5333/AD5342/AD5343 POWER-DOWN MODE The AD5332/AD5333/AD5342/AD5343 have low power con- sumption, dissipating typically 0.69 mW with supply and 1.5 mW with supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is selected by taking pin PD low. ...

  • Page 16

    ... LDAC is taken low. This means that the refer- ence buffers and the output amplifier gain of multiple DAC devices can be controlled using common GAIN and BUF lines. The AD5333 and AD5342 databuses must be at least 10, and 12 bits wide respectively, and are best suited to a 16-bit data- bus system. ...

  • Page 17

    ... A and B which, in turn, set the limits on the CMP04 signal at the V input is not within the programmed window, an LED IN will indicate the fail condition. REV. 0 AD5332/AD5333/AD5342/AD5343 Note that the AD5343 has only a single reference input. If using the AD5332, AD5333, or AD5342, both reference inputs must be connected REF REF ...

  • Page 18

    ... The circuit is shown with a 2.5 V reference, but reference volt- ages may be used. The op amps indicated will allow a DD rail-to-rail output swing. Note that the AD5343 has only a single reference input. If using the AD5332, AD5333, or AD5342, both reference inputs must be connected 0.1 F ...

  • Page 19

    ... AD5306 8 4 AD5316 10 4 AD5326 12 4 AD5307 8 4 AD5317 10 4 AD5327 12 4 Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html REV. 0 AD5332/AD5333/AD5342/AD5343 Table III. Overview of AD53xx Parallel Devices Pins Settling Time Additional Pin Functions REF BUF 6 µ µs 8 µ µ µs 7 µ µ µs 6 µ ...

  • Page 20

    ... AD5332/AD5333/AD5342/AD5343 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Thin Shrink Small Outline Package TSSOP (RU-20) 0.260 (6.60) 0.252 (6.40 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25 0.0433 (1.10) MAX 8 0.0256 (0.65) 0 0.0118 (0.30) 0.0079 (0.20) BSC ...