ADV7123 Analog Devices, ADV7123 Datasheet
ADV7123
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ADV7123 Summary of contents
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... REGISTER POWER-DOWN PSAVE MODE CLOCK GND R The ADV7123 is fabricated CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7123 is available in a 48-lead LQFP package. PRODUCT HIGHLIGHTS 1. 330 MSPS throughput. 2. Guaranteed monotonic to 10 bits. ...
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... ADV7123 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... Specifications ......................................................................... 3 3.3 V Specifications ...................................................................... Dynamic Specifications ........................................................ 5 3.3 V Dynamic Specifications ..................................................... Timing Specifications ........................................................... 7 3.3 V Timing Specifications ........................................................ 8 Absolute Maximum Ratings ............................................................ 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ...
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... Green DAC, SYNC = high RGB DAC, SYNC = low OUT Tested with DAC output = 0 V FSR = 17. MHz CLK f = 140 MHz CLK f = 240 MHz CLK R = 560 Ω SET R = 4933 Ω SET PSAVE = low, digital, and control inputs ADV7123 DD ...
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... ADV7123 3.3 V SPECIFICATIONS 1.235 REF SET Table 2. 2 Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity (BSL) Differential Nonlinearity DIGITAL AND CONTROL INPUTS Input High Voltage Input Low Voltage Input Current PSAVE Pull-Up Current Input Capacitance, C ...
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... ADV7123 Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... These maximum/minimum specifications are guaranteed by characterization over the 4. 5.25 V range. 2 Note that the ADV7123 exhibits high performance when operating with an internal voltage reference DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions. ...
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... These maximum/minimum specifications are guaranteed by characterization over the 3 3.6 V range. 2 Note that the ADV7123 exhibits high performance when operating with an internal voltage reference DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions. ...
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... ADV7123 3.3 V TIMING SPECIFICATIONS 3 3 1.235 REF SET Table 6. 3 Parameter ANALOG OUTPUTS Analog Output Delay 4 Analog Output Rise/Fall Time 5 Analog Output Transition Time 6 Analog Output Skew CLOCK CONTROL 7 CLOCK Frequency Data and Control Setup Data and Control Hold ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational + 0 section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION AA Rev Page ADV7123 ...
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... ADV7123 G5 6 TOP VIEW G6 7 (Not to Scale BLANK 11 SYNC Figure 3. Pin Configuration pins on the ADV7123 must be connected Rev Page REF 35 COMP 34 IOR 33 IOR 32 IOG 31 IOG ...
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... The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied permanently low. 38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active. ) connected between this pin and GND controls the magnitude of the full-scale video signal. SET = 530 Ω. The relationship between R ...
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... ADV7123 TYPICAL PERFORMANCE CHARACTERISTICS 5 V TYPICAL PERFORMANCE CHARACTERISTICS 1.235 17.62 mA, 50 Ω doubly terminated load, differential output loading REF OUT 70 SFDR (DE) 60 SFDR (SE 0.1 1 2.51 5.04 f (MHz) OUT Figure 4. SFDR vs 140 MHz (Single-Ended and Differential) OUT ...
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... START Figure 11. Single-Tone SFDR @ f = 140 MHz (f CLK –5 –45 –85 70MHz 0kHz STOP START = 2 MHz) Figure 12. Dual-Tone SFDR @ f OUT 70MHz STOP = 20 MHz) OUT Rev Page ADV7123 35MHz 70MHz STOP = 140 MHz (f = 13.5 MHz 14.5 MHz) CLK OUT1 OUT2 ...
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... ADV7123 3 V TYPICAL PERFORMANCE CHARACTERISTICS 1.235 17.62 mA, 50 Ω doubly terminated load, differential output loading REF OUT 70 60 SFDR (DE) SFDR (SE 1.0 2.51 5.04 20.2 f (MHz) OUT Figure 13. SFDR vs 140 MHz (Single-Ended and Differential) OUT CLK 80 SFDR (DE) ...
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... START Figure 20. Single-Tone SFDR @ f = 140 MHz (f CLK –5 –45 –85 70MHz 0kHz STOP START = 2 MHz) Figure 21. Dual-Tone SFDR @ f OUT 70MHz STOP = 20 MHz) OUT Rev Page ADV7123 35MHz 70MHz STOP = 140 MHz (f = 13.5 MHz 14.5 MHz) CLK OUT1 OUT2 ...
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... ADV7123 TERMINOLOGY Blanking Level The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch IRE units the level that shuts off the picture tube, resulting in the blackest possible picture. ...
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... All these digital inputs are specified to accept TTL logic levels. CLOCK INPUT The CLOCK input of the ADV7123 is typically the pixel clock rate of the system also known as the dot rate. The dot rate, and thus the required CLOCK frequency, is determined by the on-screen resolution, according to the following equation: Dot Rate = (Horiz Res) × ...
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... REF SET IOR, IOB (mA) = 7989.6 × V (V)/R REF Equation 1 applies to the ADV7123 only, when SYNC is being used. If SYNC is not being encoded onto the green channel, Equation 1 is similar to Equation 2. Using a variable value of R allows for accurate adjustment of SET the analog output video levels. Use of a fixed 560 Ω R yields the analog output levels quoted in the Specifications section ...
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... PCB. Alternatively, consideration can be given to using a 3- terminal voltage regulator. DIGITAL SIGNAL INTERCONNECT Isolate the digital signal lines to the ADV7123 as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7123 should be avoided to minimize noise pickup ...
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... For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV7123 to minimize reflections. Additional information on PCB design is available in the AN-333 Application Note, Design and Layout of a Video Graphics System for Reduced EMI, which is available from Analog Devices at www ...
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... ADV7123KSTZ140 −40°C to +85°C ADV7123KST140-RL −40°C to +85°C ADV7123JSTZ240 0°C to 70°C ADV7123JSTZ240-RL 0°C to 70°C ADV7123JSTZ330 0°C to 70° RoHS Compliant Part. 2 ADV7123JSTZ330 is available in a 3.3 V version only. 9.20 9.00 SQ 0.75 1.60 0.60 8.80 MAX 0. PIN 1 TOP VIEW 0.20 (PINS DOWN) 0.09 7° ...
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... ADV7123 NOTES Rev Page ...
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... NOTES Rev Page ADV7123 ...
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... ADV7123 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00215-0-7/10(D) Rev Page ...