AD7836 Analog Devices, AD7836 Datasheet
AD7836
Specifications of AD7836
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AD7836 Summary of contents
Page 1
... The AD7836 contains four 14-bit DACs on one monolithic chip. It has output voltages with a full-scale range of ± from reference voltages of ± The AD7836 accepts 14-bit parallel loaded data from the exter nal bus into one of the input latches under the control of the WR, CS and DAC channel address pins, A0– ...
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... AD7836–SPECIFICATIONS Parameter A ACCURACY Resolution 14 ± 2 Relative Accuracy ± 0.9 Differential Nonlinearity ± 8 Full-Scale Error ± 8 Zero-Scale Error ± 2 Gain Error 2 Gain Temperature Coefficient Crosstalk 50 REFERENCE INPUTS DC Input Resistance 100 ± 1 Input Current V (+) Range 0/+5 REF V (–) Range –5/0 REF [V (+) – V (– ...
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... Figure 1. Timing Diagram –3– AD7836 = –15 V 5%; AGND = DGND = 0 V) Description A0, A1 Setup Time A0, A1 Hold Time Setup Time Hold Time WR Pulsewidth Data Setup Time Data Hold Time WR Pulse Interval Settling Time ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7836 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... WR Level-Triggered Write Input (active low), when active and used in conjunction with CS to write data to the AD7836 input buffer. Data is latched into the selected data register on the rising edge of WR. DUTGND A Device Sense Ground for DAC A. Vout A is referenced to the voltage applied to this pin. ...
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... When CLR signal is brought back high the output voltages from the DACs will reflect the data stored in the relevant DAC registers. Data Loading to the AD7836 (–) = –5 V Data is loaded into the AD7836 in straight parallel 14-bit wide REF words. The DAC output voltages, V reflect new data in the DAC input registers. ...
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... TEMPERATURE – °C Figure 5. Typical DNL Error vs. Temperature 0.7 VERT = 100mV/DIV 0.6 HORIZ = 1 s/DIV 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 Figure 8. Typical Digital/Analog Glitch Impulse REV. A Typical Performance Characteristics–AD7836 0.9 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0 INPUT CODE/1000 Figure 3. Typical DNL Plot 15V ...
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... V REF REF For V (+) = +5 V, and V REF = 20 V/16384 = 1220 µV. ) CONTROLLED POWER-ON OF THE OUTPUT STAGE OUT A block diagram of the output stage of the AD7836 is shown (16383/16384) V REF Figure 13 capable of driving a load of 5 kΩ in parallel 2 V (8192/16384) V REF with 50 pF ...
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... V OUT Figure 16. Output Stage After CLR Is Taken High Power-On with CLR High If CLR is high on the application of power to the device, the output stages of the AD7836 are configured as in Figure 17 while thereby connecting the output of the DAC to the input of its output amplifier. G < ...
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... Digital and analog ground planes should only be joined at one place. If the AD7836 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7836 ...
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... V The AD7836 uses nominal reference values of ± achieve DEVICE OUT GND an output span of ± Since the AD7836 has a gain of two C OUT from the reference inputs to the DAC output, adjusting the ref- DEVICE erence voltages by ± 150 mV will adjust the DAC offset and ...
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... SCLK LOGIC LEVEL CONTROLLER DATA BUS Figure 22. Programmable Reference Generation for the AD7836 the digital signals driving the DACs need to be level shifted from the range to the – range. Figure 22 shows a typical application circuit to provide programmable ref- erence capabilities for the AD7836 ...