ADP5065

Manufacturer Part NumberADP5065
DescriptionFast Charge Battery Management with Power Path and USB Compatibility
ManufacturerAnalog Devices
ADP5065 datasheet
 


Specifications of ADP5065

Product DescriptionFast Charge Battery Management with Power Path and USB CompatibilitySwitching/linearSwitching
Cell TypeLi-IonFinal Voltage Options4.2
Accuracy Over Temp (%)0.3%Temp Range-40 to +125°C
PackageWLCSP-20Active For Param SearchYes
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Data Sheet
FEATURES
3 MHz switch mode charger
1.25 A charge current from dedicated charger
Up to 680 mA charging current from 500 mA USB host
Operating input voltage from 4.0 V up to 5.5 V
Tolerant input voltage −0.5 V to +12 V (USB VBUS)
Dead battery isolation FET between battery and
charger output
Battery thermistor input with automatic charger shutdown
for when battery temperature exceeds limits
Compliant with the JEITA Li-Ion battery charging
temperature specification
SYS_EN_OK flag to hold off system turn-on until battery is at
minimum required level for guaranteed system startup
due to minimum battery voltage and/or minimum battery
charge level requirements
EOC programming with C/20, C/10 and specific current level
selection
APPLICATIONS
Digital still cameras
Digital video cameras
Single cell Li-Ion portable equipment
PDA, audio, GPS devices
Mobile phones
GENERAL DESCRIPTION
The
ADP5065
charger is fully compliant with the USB 2.0,
USB 3.0, and USB Battery Charging Specification 1.1 and
enables charging via the mini USB VBUS pin from a wall
charger, car charger, or USB host port.
The
ADP5065
operates from a 4 V to 5.5 V input voltage range
but is tolerant of voltages of up to 12 V. This alleviates the
concerns about the USB bus spiking during disconnect or
connect scenarios.
The
ADP5065
also features an internal FET between the dc-to-
dc charger output and the battery. This permits battery isolation
and, hence, system powering under a dead battery or no battery
scenario, which allows for immediate system function on
connection to a USB power supply.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Fast Charge Battery Manager with Power
Path and USB Compatibility
FUNCTIONAL BLOCK DIAGRAM
AC
VBUS
VINx
OR
USB
CFILT
IIN_EXT
TRK_EXT
SCL
SDA
SYS_ON_OK
V_WEAK_SET
Based on the type of USB source, which is detected by an external
USB detection chip, the
current limit for optimal charging and USB compliance.
The
ADP5065
comes in a very small and low profile 20-lead
WLCSP (0.5 mm pitch spacing) package.
The overall solution requires only five small, low profile external
components consisting of four ceramic capacitors (one of which
is the battery filter capacitor), one multilayer inductor. In addition
to these components, there is one optional dead battery situation
default setting resistor. This configuration enables a very small
PCB area to provide an integrated and performance enhancing
solution to USB battery charging and power rail provision.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
ADP5065
ADP5065
SYSTEM
SWx
INDUCTOR
3MHz
PGNDx
BUCK
ISO_Sx
ISO_Bx
CHARGER
CONTROL
BAT_SNS
BLOCK
+
Li-Ion
THR
AGND
PGNDx
Figure 1.
ADP5065
can be set to apply the correct
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.

ADP5065 Summary of contents

  • Page 1

    ... This configuration enables a very small PCB area to provide an integrated and performance enhancing solution to USB battery charging and power rail provision. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ADP5065 ADP5065 SYSTEM SWx INDUCTOR 3MHz PGNDx BUCK ...

  • Page 2

    ... ADP5065 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Recommended Input and Output Capacitance........................ C-Compatible Interface Timing Specifications ..................... 6 Absolute Maximum Ratings ....................................................... 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Temperature Characteristics ..................................................... 11 Typical Waveforms ..................................................................... 13 Theory of Operation ...

  • Page 3

    ... L(PK) V 3.21 3.3 3.39 ISO_STRK 5 R 220 285 DS(ON)P R 160 210 DS(ON)N Rev Page ADP5065 = 2.2 μ μ μF, C VIN DCDC BAT Unit Test Conditions/Comments V Falling threshold, higher of V and V CFILT mV Hysteresis, higher of V and V CFILT BAT_SNS mA Nominal USB initialized current level ...

  • Page 4

    ... ADP5065 Parameter BATTERY ISOLATION FET Bump to Bump Resistance Between ISO_Bx and ISO_Sx Bumps Regulated System Voltage Battery Supplementary Threshold HIGH VOLTAGE BLOCKING FET VINx Input High Voltage Blocking FET On Resistance Current, Suspend Mode Input Voltage Good Threshold Rising Falling Overvoltage Threshold ...

  • Page 5

    ... BUS Min Typ Max Unit 1.0 μF 2.0 4.7 5.0 μ μF 10 μF Rev Page ADP5065 Unit Test Conditions/Comments °C Battery termination voltage ( reduced TRM by 100 mV Ω Ω °C No battery charging occurs ≥ 3.7 V, valid after charge complete (see ...

  • Page 6

    ... ADP5065 2 I C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS Table 3. 1 Parameter I 2 C-COMPATIBLE INTERFACE 2 Capacitive Load, Each Bus Line SCL Clock Frequency SCL High Time SCL Low Time Data Setup Time Data Hold Time Setup Time for Repeated Start Hold Time for Start/Repeated Start ...

  • Page 7

    ... ADP5065. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in the silicon devices that potentially cause failure. ...

  • Page 8

    ... ADP5065 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin 1 No. Name Type Description D3, E3 SW1, SW2 I/O DC-to-DC Converter Inductor Connection. These pins are high current outputs when in charging mode. D1, E1 VIN1, VIN2 I/O Power Connection to USB VBUS. These pins are high current inputs when in charging mode. ...

  • Page 9

    ... Figure 9. USB Limited Battery Charge Current vs. Battery Voltage, Rev Page 100 0.01 0.1 SYSTEM OUTPUT CURRENT (A) 4.5 4.3 4.1 3.9 3.7 3.5 SYSTEM VOLTAGE 3.3 3.1 2.9 BATTERY VOLTAGE 2.7 2.5 2.7 3.0 3.3 3.6 BATTERY VOLTAGE (V) = 5.0 V, ILIM = 100 mA IN 140 120 100 2.7 3.0 3.3 3.6 BATTERY VOLTAGE ( 5.0 V, ILIM = 100 mA IN ADP5065 3.9 4.2 3.9 4.2 ...

  • Page 10

    ... ADP5065 100 2.7 3.0 3.3 3.6 BATTERY VOLTAGE (V) Figure 10. Battery Isolation FET Resistance vs. Battery Voltage, V Load Current = 1.0 A 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 VIN VOLTAGE (V) Figure 11. VINx Current vs. VINx Voltage, Suspend Mode (EN_CHG = 0) 4.4 I ISO_B 4.2 4.0 3.8 3.6 3.4 3.2 3.0 3.9 4 5.0 V, Figure 12. Charge Profile Rev Page Data Sheet ...

  • Page 11

    ... TRM –40 – AMBIENT TEMPERATURE (°C) Programming 3.50 V, 3.80 V, 4.20 V, and 4.42 V –40 – AMBIENT TEMPERATURE (°C) –40 – AMBIENT TEMPERATURE (° 1050 mA IN ISO_B CHG ADP5065 100 120 = 5 TRM 100 120 = 5 100 120 ...

  • Page 12

    ... ADP5065 1 2.7V ISO_B 0 3.6V ISO_B V = 4.2V ISO_B 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –40 – AMBIENT TEMPERATURE (°C) Figure 19. Battery Leakage Current vs. Ambient Temperature 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 –40 – AMBIENT TEMPERATURE (°C) Figure 20. VINx Quiescent Current vs. Temperature, V Suspend Mode (EN_CHG = 5 Rev Page 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 AMBIENT TEMPERATURE (°C) Figure 21 ...

  • Page 13

    ... A CH3 44mA T 0.00s Impedance, ILIM = 100 ISO_B I VIN V ISO_S V IN CH2 2.0V 100µs A CH3 40mA T 0.00s High), ILIM = 500 mA Ω LOAD T V ISO_S 800ns A CH1 2.16V W CH4 500mA T –8.0ns = 5 1000 mA IN ISO_S ADP5065 ...

  • Page 14

    ... ADP5065 T V ISO_S ISO_S 4 B CH1 100mV 200µs W CH4 500mA T 600.0µs Figure 28. System Voltage Load Transient AND C ISO_B ISO_S INRUSH CURRENT I ISO_B 3 V ISO_S 2 CH2 2.0V 100µs CH3 2.0A T 0.00s Figure 29. Battery Connect CH4 250mA = 5 Battery Figure 30 ...

  • Page 15

    ... Fast charge safety timer period. • Watchdog safety timer parameters. • Weak battery threshold detection. • Charge complete threshold. • Recharge threshold. • Charge enable/disable. • Battery pack temperature detection and automatic charger shutdown. Rev Page ADP5065 ADP5065 can be set ...

  • Page 16

    ... ADP5065 TO USB VBUS VIN1 OR WALL D1 ADAPTER VIN2 E1 + 5.42V – VIN OVERVOLTAGE + 3.9V – VIN GOOD INTERFACE SCL AND A2 CONTROL LOGIC SDA B1 IIN_EXT A4 TRK_EXT B2 V_WEAK_SET A1 + 0.5V – SYS_ON_OK D2 SYSTEM VOLTAGE OK LOGIC E2 HIGH VOLTAGE BLOCKING FET HV-FET + CONTROL DC-DC CONTROL VIN LIMIT – 3MHz OSC ...

  • Page 17

    ... The fault condition is asserted on the CHARGER_STATUS register, allowing the user to initiate the fault recovery procedure specified in the Fault Recovery section. Rev Page Standard USB Limit ADP5065 Function 100 mA limit for stan- 100 mA input current limit 2 dard USB host or hub ...

  • Page 18

    ... BAT_SNS pin. TRM without the voltage at the BAT_SNS pin CHG , a fault condition is assumed and charging stops. TRM , charging stops. No fault condi- END ADP5065 charger features a programmable watchdog charger determines that the processor should be . When the watchdog WEAK . WD ADP5065 charger assumes there is a software ...

  • Page 19

    ... The ADP5065 ADP5065 threshold detector. If the die temperature exceeds T ADP5065 is set The ADP5065 LIM , temperature drops below the T SAFE 140°C bit is reset. To reset the TSD 140°C bit, write to the I Fault Register 0x0D or cycle the power. Before die temperature reaches T set exceeded ...

  • Page 20

    ... BATOK ADP5065 within the specified timeout period the linear regulator. , either the battery voltage is low or the battery BATH after t BAT_SHR ADP5065 assumes that the battery node is shorted. Data Sheet charger moni fault is BAT_SHR has BAT_SHR ...

  • Page 21

    ... STATUS t BAT_OK OPEN OR SHORT Figure 32. Battery Detection Sequence SOURCE PHASE V BATH LOGIC STATUS t BAT_OK SHORT OR LOW BATTERY ISO_Bx Figure 33. Battery Short Detection Sequence Rev Page ADP5065 V LOGIC BATH STATUS t BAT_OK OPEN ISO_Bx TRICKLE CHARGE V BAT_SHR LOGIC STATUS t BAT_SHR SHORT ISO_Bx ...

  • Page 22

    ... Fuse-selectable beta programming is supported by eight steps covering a range from 3150 to 4400 (see Table 34). JEITA Li-Ion Battery Temperature Charging Specification The ADP5065 charging temperature specifications as outlined in Table 11. THR Function The JEITA function can be enabled via the I Off ...

  • Page 23

    ... Threshold N (3.0 V default) 13.2 2.7 V 17.8 2.8 V 23.5 2.9 V 31.0 3.0 V 41.3 3.1 V 56.2 3.2 V 79.7 3.3 V 122.4 3.4 V Rev Page threshold can be programmed set either by I WEAK to obtain its default value. WEAK Voltage V Voltage WEAK WEAK (Falling Threshold programmed − 100 mV 2.6 V 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 3.2 V 3.3 V ADP5065 ...

  • Page 24

    ... ADP5065 RECEIVES DATA 0 0 ADP5065 RECEIVES ADP5065 RECEIVES DATA TO REGISTER DATA TO LAST REGISTER 1 = READ CHIP ADDRESS ADP5065 SENDS DATA 0 0 ADP5065 SENDS DATA OF REGISTER Data Sheet ADP5065 MASTER STOP MASTER STOP ADP5065 SENDS ...

  • Page 25

    ... Operational Flowchart Rev Page START EXPIRED POWER DOWN N IBUSLIM = HIGH N LIM VIN LIM THERMLIM = HIGH N TEMP = T LIM LIM WATCHDOG Y EXPIRED t START SAFE I = 100mA BUS TFAULT BAD BATTERY CHG (SEE TIMER SECTION) N CC-MODE = CHARGING N CV-MODE END CHARGING ADP5065 ...

  • Page 26

    ... ADP5065 REGISTER MAP 2 1 Table 14 Register Map Register D7 D6 Addr. Name 0x00 Manufac- turer and model ID 0x01 Silicon revision 0x02 VINx pins settings 0x03 Termina- tion settings 0x04 Charging C/20 EOC C/10 EOC current 0x05 Voltage threshold 0x06 Timer settings 0x07 ...

  • Page 27

    ... Rev Page ADP5065 ...

  • Page 28

    ... ADP5065 Table 18. Termination Settings, Register Address 0x03 Bit Descriptions Bit No. Mnemonic Access [7:2] VTRM[5:0] R/W Default Description 100011 = 4.20 V Termination voltage programming bus. The values of the float voltage can be programmed as per the following values: 000000 = 3.50 V. 000001 = 3.52 V. 000010 = 3.54 V. 000011 = 3.56 V. 000100 = 3.58 V. 000101 = 3.60 V. 000110 = 3.62 V. 000111 = 3.64 V. 001000 = 3.66 V. 001001 = 3.68 V. ...

  • Page 29

    ... V Trickle to fast charge dead battery voltage programming bus. The values of the trickle to fast charge threshold can be programmed as per following values 3.3 V. Rev Page ADP5065 ...

  • Page 30

    ... ADP5065 Bit No. Mnemonic Access [2:0] VWEAK[1:0] R/W Table 21. Timer Settings, Register Address 0x06 Bit Descriptions Bit No. Mnemonic Access [7:6] Not used 5 EN_TEND R/W 4 EN_CHG_TIMER R/W 3 CHG_TMR_PERIOD R/W 2 EN_WD R PERIOD R/W 0 RESET_WD W Table 22. Functional Settings1, Register Address 0x07 Bit Descriptions Bit No. Mnemonic Access 7 EN_JEITA R/W 6 DIS_IPK_SD R/W 5 EN_BMON R/W 4 EN_THR R/W 3 Not used ...

  • Page 31

    ... Charger status bus. 000 = off. 001 = trickle charge. 010 = fast charge (CC mode). 011 = fast charge (CV mode). 100 = charge complete. 101 = suspend. 110 = trickle or fast charge timer expired. 111 = battery detection. Rev Page ADP5065 . CHG but is limited by the die temperature. CHG ...

  • Page 32

    ... ADP5065 Table 27. Charger Status Register 2, Register Address 0x0C Bit Descriptions Bit No. Mnemonic Access [7:5] THR_STATUS[2: IPK_STAT R 3 Not Used R [2:0] BATTERY_STATUS[2:0] R Table 28. Fault Register, Register Address 0x0D Bit Descriptions Bit No. Mnemonic Access [7:4] Not Used 3 BAT_SHR R/W 2 IND_PEAK_INT R/W 1 TSD 130°C R/W 0 TSD 140°C ...

  • Page 33

    ... EMI. ISO_Sx (V ) and ISO_Bx Capacitor Selection OUT To safely obtain stable operation of the ADP5065, the ISO_Sx and ISO_Bx effective capacitance (including temperature and dc bias effects) must not be less than 10 μF at any point during operation. The combined effective capacitance of the ISO_Sx capacitor and the system capacitance must not exceed 50 μ ...

  • Page 34

    ... VINx and CFILT pins must not exceed 10 μF at any tempera- ture or dc bias condition. Suggestions for a VINx capacitor is given in Table 32. CFILT Capacitor Selection CFILT pin serves the ADP5065 as the step-down dc-to-dc converter input capacitor. Maximum input capacitor current is calculated using the following equation: V ...

  • Page 35

    ... ISO_S2 DC-DC) SCL A2 CHARGE CONTROL ISO_B1 (CHARGE MODE, SDA B1 BATTERY ISOLATION) IIN_EXT A4 ISO_B2 TRK_EXT B2 BAT_SNS THR V_WEAK_SET A1 SYS_ON_OK Figure 40. Reference Circuit Diagram Rev Page 1µH LQH32PN1R0NN0 CONNECT CLOSE TO BATTERY + C1 A3 VDDIO R4 10kΩ MCU ADP5065 ...

  • Page 36

    ... ADP5065 ADP5065 V IN PGND C 4.7µF CFILT PGND 11.5mm Figure 41. PCB Layout Suggestion Rev Page 22µF PGND ISO_B Data Sheet ...

  • Page 37

    ... A second method to estimate the power dissipation uses the system voltage and charging efficiency curves provided for the ADP5065. When the efficiency is known, use Equation 3b to derive the total power lost in the dc-to-dc converter, isolation FET and inductor; use Equation 5 to derive the power lost in ...

  • Page 38

    ... ADI Reliability Handbook at the following URL: www.analog.com/reliability_handbook Rev Page Data Sheet ) can also be calculated J ) and power dissipation ( × θ the junction-to-board thermal resistance based on a 4-layer × 3 in, 2.5 oz copper JB ADP5065 . ) D (10) (Equation 9) ...

  • Page 39

    ... Data Sheet FACTORY-PROGRAMMABLE OPTIONS Table 34. ADP5065 Fuse-Selectable Trim Options Parameter NTC Thermistor Type NTC Beta Value ADP5065ACBZ-1-R7 Trim Setting 10 kΩ 10 kΩ 100 kΩ 3150 3350 3350 3500 3650 3850 4000 4200 4400 Rev Page ADP5065 ...

  • Page 40

    ... COPLANARITY 0.04 0.360 0.270 0.320 0.240 0.280 0.210 Figure 42. 20-Ball Wafer Level Chip Scale Package [WLCSP] (CB-20-8) Dimensions shown in millimeters Package Description 20-Ball Wafer Level Chip Scale Package [WLCSP] ADP5065 Evaluation Board Rev Page Data Sheet BOTTOM VIEW (BALL SIDE UP) 1 ...