ADM1060 Analog Devices, ADM1060 Datasheet
ADM1060
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ADM1060 Summary of contents
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... Either the VH supply or one of the VPn supplies is used to DD power the ADM1060 (whichever is highest). This ensures that in the event of a supply failure, the ADM1060 is kept alive for as long as possible, thus enabling a reliable fault flag to be asserted and the system to be powered down in an ordered fashion. ...
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... ADM1060 TABLE OF CONTENTS General Description ......................................................................... 3 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 7 Typical Performance Characteristics ............................................. 8 Inputs................................................................................................ 11 SFD REGISTER NAMES........................................................... 14 SFD Register Bit Maps ............................................................... 15 Programming .................................................................................. 21 Logic ................................................................................................. 22 PLBA REGISTER BIT MAPS ................................................... 28 Outputs ............................................................................................ 33 REVISION HISTORY 12/03—Data sheet changed from Rev Rev. B Changes to Specifications ............................................................................. Changes to Outputs section............................................................33 Updated Outline Dimensions.........................................................50 5/03— ...
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... All of the inputs and outputs described previously are controlled by the programmable logic block array (PLBA). This is the logic core of the ADM1060 comprised of nine macrocells, one for each PDO. These macrocells are essentially just wide AND gates. Any/all of the inputs can be used as an input to these macrocells ...
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... ADM1060 ADM1060 HIGH SUPPLY VH 8 (14.4V) FAULT DETECTOR POSITIVE VP1 9 SUPPLY FAULT DETECTOR 1 VP2 10 VP3 11 VP4 POSITIVE 12 SUPPLY FAULT DETECTOR 4 BIPOLAR VB1 13 SUPPLY FAULT DETECTOR 1 BIPOLAR VB2 14 SUPPLY FAULT DETECTOR 2 GPI1 28 INPUT LOGIC GPI2 27 SIGNAL CONDITION GPI3 26 GPI4 25 WATCHDOG WDI 24 FAULT DETECTOR ...
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... kΩ µA Rev Page ADM1060 Test Conditions/Comments Any VPn ≥ 3 ≥ 4.75 V Any VPn = 6 14.4 V VDDCAP = 4. PDO FET drivers on, no loaded PDO pull-ups to VDDCAP VDDCAP = 4.75 V, all PDO FET drivers on (loaded with 1 µA), no PDO pull-ups to VDDCAP Max additional load that can be drawn from PDO ...
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... ADM1060.program@analog.com = 3 required 0°C to +85°C and a minimum 55°C as per JEDEC Std. 22 method A117 0.8 V for a falling edge and V = 2.0 V for a rising edge Rev Page Test Conditions/Comments V V µ 5 µ ...
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... Exposure to absolute –0 +6.5 V maximum rating conditions for extended periods may affect ±5 mA device reliability. ±20 mA THERMAL CHARACTERISTICS 150°C –65°C to +150°C 28-Lead TSSOP Package: θ = 98°C/W JA 215°C 2000 V Rev Page ADM1060 ...
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... ADM1060 TYPICAL PERFORMANCE CHARACTERISTICS 6 VP1 (V) VH, VP1 Figure 2. V vs. V and V VDDCAP VH 3.0 2.5 2.0 1.5 1.0 0 (V) VP1 Figure 3. I vs. V (Supply) DD VP1 300 250 200 150 100 (V) VP1 Figure 4. I vs. V (Not Supply) ...
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... Figure 11. V 1.00 0.75 0.50 0. Figure 12. V 2.0 1 VP1 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 Figure 13. V Rev Page ADM1060 VP1 V = 3.3V VP1 (µA) LOAD (Weak Pull-Up to VP1) vs. Load Current PDO (mA) LOAD (Strong Pull-Down) vs. Load Current PDO ...
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... ADM1060 110 108 106 104 102 100 –40 –25 – TEMPERATURE (°C) Figure 14. Oscillator Frequency vs. Temperature 6.00 5.75 5.50 V 5.25 5.00 V 4.75 4.50 0 100 200 I (µA) LOAD Figure 15. VCCP vs. Load Current 3.0 2.5 2.0 1.5 1.0 0.5 0 –40 –25 – TEMPERATURE (°C) Figure 16. GPI Threshold vs. Temperature 4.75V VDDCAP = 2 ...
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... This loss can be reduced to ~0.2 V, resulting in the ability to power the ADM1060 from a supply as low as 3.0 V. Note that the supply on the VBn pins cannot be used to power the device, even if the input on these pins is positive. Also, the minimum supply of 3 ...
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... VBn. Only one range (− − available when the SFDs are in negative mode. Note that the bipolar SFDs cannot be used to power the ADM1060, even if the voltage on VBn is positive. Rev Page ...
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... The tables show how to set up UV threshold, UV hysteresis, OV threshold, OV hysteresis, glitch filtering, and fault type for each of the SFDs on the ADM1060. Rev Page ADM1060 PROGRAMMED TIMEOUT ...
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... ADM1060 SFD REGISTER NAMES Table 4. List of Registers for the Supply Fault Detectors Hex Address Table Name A0 Table 5 BS1OVTH A1 Table 6 BS1OVHYST A2 Table 7 BS1UVTH A3 Table 8 BS1UVHYST A4 Table 9 BS1SEL A8 Table 5 BS2OVTH A9 Table 6 BS2OVHYST AA Table 7 BS2UVTH AB Table 8 BS2UVHYST AC Table 9 BS2SEL B0 Table 10 HSOVTH B1 Table 11 HSOVHYST B2 Table 12 ...
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... FS0 Fault Select Type 0 Overvoltage 1 Undervoltage 0 Out-of-Window 1 Not Allowed Rev Page ADM1060 R/W Description R/W 8-Bit Digital Value for UV Thresh- old on BSn SFD R/W Description N/A Cannot Be Used R/W 5-Bit Digital Value for Hysteresis on UV Threshold of BSn SFD Glitch Filter Delay (µs) ...
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... ADM1060 HIGH VOLTAGE SUPPLY FAULT DETECT (HV SFD) REGISTERS Table 10. Register 0xB0 HSOVTH (Power-On Default 0xFF) Bit Name R/W Description 7–0 OV7–OV0 R/W 8-Bit Digital Value for OV Threshold on HV SFD Table 11. Register 0xB1 HSOVHYST (Power-On Default 0x00) Bit Name R/W Description 7–5 Reserved N/A Cannot Be Used 4– ...
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... UV7−UV0 R/W 8-Bit Digital Value for UV Thresh- old on PSn SFD Name W Description Reserved N/A Cannot Be Used HY4−HY0 R/W 5-Bit Digital Value for Hysteresis on UV Threshold of PSn SFD Glitch Filter Delay (µ 100 Top of Range Step Size (mV 15 7.8 1.8 V 4.7 ADM1060 ...
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... ADM1060 WATCHDOG FAULT DETECTOR The ADM1060 has a watchdog fault detector. This can be used to monitor a processor clock to ensure normal operation. The detector monitors the WDI pin, expecting a low-to-high or high-to-low transition within a preprogrammed period. The watchdog timeout period can be programmed from 200 maximum of 12 ...
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... PWRGOOD signals, fault flags, manual resets, and so on. These signals can be gated with the other inputs supervised by the ADM1060 and used to control the status of the PDOs. The inputs can be simply buffered logic transition can be detected and a pulse output generated. The width of this pulse is programmable from 10 µ ...
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... ADM1060 Table 24. Registers for the Pull-Down Current Sources on Logic Inputs Hex Address Name Default Power On Value 91 PDEN 0x00 Table 25. PDEN Register 0x91 Bit Map (Power-On Default 0x00) Bit Name R/W Description 7 Reserved N/A Cannot Be Used 6 PDENA1 R/W If high, address pin A1 is pulled to GND using a 10 µA pull-down current source. ...
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... This block is the logical core of the device. The PLBA (and the PDBs—see the Programmable Delay Block section) provides the sequencing function of the ADM1060. The asser- tion of the nine programmable driver outputs (PDO) is controlled by the PLBA. The PLBA is comprised of nine macro- cells, one per PDO channel ...
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... ADM1060 LOGIC NOT CONNECTED PLB1 PLB2 INVERT 0x00 P1PLBPOLA.0 IGNORE 0x01 P1PLBIMKA.0 PLB3 INVERT 0x00 P1PLBPOLA.1 IGNORE 0x01 P1PLBIMKA.1 PLB4 INVERT 0x00 P1PLBPOLA.2 IGNORE 0x01 P1PLBIMKA.2 PLB5 INVERT 0x00 P1PLBPOLA.3 IGNORE 0x01 P1PLBIMKA.3 PLB6 INVERT 0x00 P1PLBPOLA.4 IGNORE 0x01 P1PLBIMKA.4 PLB7 INVERT 0x00 P1PLBPOLA ...
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... Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A function of PLB2 0x00 Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A function of PLB2 0x00 Polarity sense and ignore mask bits for all four GPIs when used as inputs to the A function of PLB2 Rev Page ADM1060 ...
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... ADM1060 Hex Address Table Name 15 Table 34 P2GPIIMK 16 Table 35 P2WDICFG 17 Table 36 PS2EN 18 Table 29 P2PLBPOLB 19 Table 30 P2PLBIMKB 1A Table 31 P2SFDPOLB 1B Table 32 P2SFDIMKB 20 Table 29 P3PLBPOLA 21 Table 30 P3PLBIMKA 22 Table 31 P3SFDPOLA 23 Table 32 P3SFDIMKA 24 Table 33 P3GPIPOL 25 Table 34 P3GPIIMK 26 Table 35 P3WDICFG 27 Table 36 PS3EN 28 Table 29 P3PLBPOLB 29 Table 30 P3PLBIMKB 2A Table 31 P3SFDPOLB ...
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... Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B function of PLB6 0x00 Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B function of PLB6 0x00 Polarity sense for all eight other PLB outputs when used as inputs to the A function of PLB7 Rev Page ADM1060 ...
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... ADM1060 Hex Address Table Name 61 Table 30 P7PLBIMKA 62 Table 31 P7SFDPOLA 63 Table 32 P7SFDIMKA 64 Table 33 P7GPIPOL 65 Table 34 P7GPIIMK 66 Table 35 P7WDICFG 67 Table 36 PS7EN 68 Table 29 P7PLBPOLB 69 Table 30 P7PLBIMKB 6A Table 31 P7SFDPOLB 6B Table 32 P7SFDIMKB 70 Table 29 P8PLBPOLA 71 Table 30 P8PLBIMKA 72 Table 31 P8SFDPOLA 73 Table 32 P8SFDIMKA 74 Table 33 P8GPIPOL 75 Table 34 P8GPIIMK 76 Table 35 P8WDICFG ...
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... Ignore mask for all eight other PLB outputs when used as inputs to the B function of PLB9 0x00 Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B function of PLB9 0x00 Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B function of PLB9 Rev Page ADM1060 ...
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... ADM1060 PLBA REGISTER BIT MAPS Table 29. PnPLBPOLA/PnPLBPOLB Registers Bit Map (Power-On Default 0x00) Bit Name R/W Description 7–0 POL9−POL1 R/W If high, invert the PLBn input before it is used in function PLB1 Function A 0x00 Function B 0x08 7 PLB9 6 PLB8 5 PLB7 4 PLB6 3 PLB5 2 PLB4 1 PLB3 ...
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... GPI4 GPI4 GPI1 GPI1 GPI1 GPI1 GPI2 GPI2 GPI2 GPI2 GPI3 GPI3 GPI3 GPI3 GPI4 GPI4 GPI4 GPI4 Rev Page ADM1060 PLB6 PLB7 PLB8 PLB9 0x53 0x63 0x73 0x83 0x5B 0x6B 0x7B 0x8B VP4 VP4 VP4 VP4 VP3 VP3 VP3 ...
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... ADM1060 Table 34. PnGPIIMK Registers Bit Map (Power-On Default 0x00) Bit Name R/W Description 7−4 AIMK4−AIMK1 R/W If high, mask the GPIn input before it is used in function A. 3−0 BIMK4−BIMK1 R/W If high, mask the GPIn input before it is used in function B. PLB1 0x05 7 GPI1 Function A ...
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... RISE 1 FALL RISE 1 FALL PDB OUTPUT PROGRAMMING RISE TIME AND FALL TIME Figure 22. Programmable Delay Block (PDB) Functionality Rev Page ADM1060 PROGRAMMED PROGRAMMED RISE TIME FALL TIME = RISE FALL RISE FALL PROGRAMMED PROGRAMMED ...
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... ADM1060 Table 37. Programmable Delay Block (PDB) Registers Default Hex Power-On Addr. Table Name Value 0C Table 38 P1PDBTIM 0x00 1C Table 38 P2PDBTIM 0x00 2C Table 38 P3PDBTIM 0x00 3C Table 38 P4PDBTIM 0x00 4C Table 38 P5PDBTIM 0x00 5C Table 38 P6PDBTIM 0x00 6C Table 38 P7PDBTIM 0x00 7C Table 38 P8PDBTIM 0x00 8C Table 38 P9PDBTIM 0x00 Table 38 ...
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... OUTPUTS PROGRAMMABLE DRIVER OUTPUTS The ADM1060 has nine programmable driver outputs (PDOs). These are the logic outputs of the device. Each PDO is normally controlled by a single PDB. Thus, the PDOs can be set up to assert when the conditions on the PDB are met, such as when the SFDs are in tolerance, the levels on the GPI are correct, the watchdog timer has not timed out, and so on ...
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... ADM1060 Table 39. Programmable Driver Outputs Registers Hex Address Table Name 0D Table 40 P1PDOCFG 1D Table 40 P2PDOCFG 2D Table 40 P3PDOCFG 3D Table 40 P4PDOCFG 4D Table 40 P5PDOCFG 5D Table 40 P6PDOCFG 6D Table 40 P7PDOCFG 7D Table 40 P8PDOCFG 8D Table 40 P9PDOCFG Table 40. PnPDOCFG Register 0x0D, 0x1D, 0x2D, 0x3D, 0x4D, 0x5D, 0x6D, 0x7D, 0x8D (Power-On Default 0x00) ...
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... This is achieved by providing a “fault plane” consisting of two registers, LATF1 and LATF2, that the system controller can read out of the ADM1060 via the SMBus. Each bit in the two registers (with one important exception, see below) is assigned to one of the inputs of the devices as shown in Table 41 ...
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... ADM1060 The functionality of the fault plane is best illustrated with an example. For instance, take VP1 to have an input supply of 5 UV/OV window set up on VP1. The supply is ramped in and out of this window, each time reading the contents of LATF1 and LATF2. The values recorded are as follows: 1 ...
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... Logic level currently being driven on PDO2 output. 0 PDO1STAT R Logic level currently being driven on PDO1 output. Table 48. Bit Map for PDOSTAT2 Register 0xDF (Power-On Default 0x00) Bit Name R/W Description 7–1 Reserved N/A Cannot Be Used 0 PDO9STAT R Logic level currently being driven on PDO9 output. Rev Page ADM1060 ...
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... ADM1060 FAULT REGISTERS Table 49. List of Fault Registers Hex Addr. Table Name Default Power On Value DC Table 50 LATF1 0x00 DD Table 51 LATF2 0x00 Table 50. Bit Map for LATF1 Register 0xDC (Power-On Default 0x00) Bit Name R/W Description 7 ANYFLT R If high, a change in logic status (fault) has been logged on one of the 12 functions monitored since the last time the Fault Registers were read ...
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... If high, a change in the logic level on the GPI2 input is ignored and not logged in LATF2. 0 GPI1MASK R/W If high, a change in the logic level on the GPI1 input is ignored and not logged in LATF2. Description Error Mask Register for the seven SFDs Error Mask Register for the four GPIs and the Watchdog Detector Rev Page ADM1060 ...
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... EEPROM into the RAM registers, the user may wish to alter the configuration of functions on the ADM1060; for example, change the limit of an SFD, the fault output of an SFD, the timeout of the watchdog detec- tor, the rise time delay of one of the PDOs, and so on. ...
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... If set high, the ADM1060 will download the buffered RAM register data into the local latches. This bit self-clears (returns to 0) after the download. 0 UPD R/W If set high, the ADM1060 will update its configuration in real time as a word is written to a local RAM register via the SMBus. CONTROLLER POWER-UP (V > ...
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... This may be used for permanent storage of data that will not be lost when the ADM1060 is pow- ered down, unlike the data in the volatile registers. Although referred to as read-only memory, the EEPROM can be written to (as well as read from) via the serial bus in exactly the same way as the other registers ...
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... BUF P S SMBus PROTOCOLS FOR RAM AND EEPROM The ADM1060 contains volatile registers (RAM) and nonvola- tile EEPROM. User RAM occupies address locations from 0x00 to 0xDF, while EEPROM occupies addresses from 0xF800 to 0xF9FF. Data can be written to and read from both RAM and EEPROM as single data bytes ...
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... The slave asserts ACK on SDA. 10. The master asserts a STOP condition on SDA to end the transaction the ADM1060, the write byte/word protocol is used for three A P purposes write a single byte of data to RAM. In this case the com- mand byte is the RAM address from 0x00 to 0xDF and the (only) data byte is the actual data ...
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... In this operation, the master device writes a block of data to a slave device. The start address for a block write must previously have been set. In the case of the ADM1060, this is done by a Send Byte operation to set a RAM address or a Write Byte/Word operation to set an EEPROM address. ...
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... In this operation, the master device reads a block of data from a slave device. The start address for a block read must previously have been set. In the case of the ADM1060, this is done by a Send Byte operation to set a RAM address Write Byte/Word operation to set an EEPROM address. The block ...
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... PDO6 20 PDO7 21 28 GPI1 PDO8 22 27 GPI2 GPI3 23 26 PDO9 25 GPI4 24 WDI A0 A1 SDA SCL 3.3V VIN CONVERTER EN VIN VOUT INVERTER Figure 37. ADM1060 Application Diagram Rev Page ADM1060 5V_OUT 5VSB_OUT 3.3V_OUT 3.3VSB_OUT PWR_OK ACK CLKOUT EN 1.8V VIN_CORE VOUT DC/DC µP –5V_OUT ...
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... ADM1060 Table 57. ADM1060 Register Map BLOCK PLB1 0 P1PLBPOLA P1PLBIMKA P1SFDPOLA PLB2 1 P2PLBPOLA P2PLBIMKA P2SFDPOLA PLB3 2 P3PLBPOLA P3PLBIMKA P3SFDPOLA PLB4 3 P4PLBPOLA P4PLBIMKA P4SFDPOLA 4 P5PLBPOLA P5PLBIMKA P5SFDPOLA PLB5 PLB6 5 P6PLBPOLA P6PLBIMKA P6SFDPOLA PLB7 6 P7PLBPOLA P7PLBIMKA P7SFDPOLA PLB8 7 P8PLBPOLA P8PLBIMKA P8SFDPOLA PLB9 8 P9PLBPOLA ...
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... VB1 PDO2 13 16 VB2 PDO1 14 15 Figure 38. Pin Configuration arbitrator will select this supply to power the ADM1060 the highest DD arbitrator will select one of these supplies to power the ADM1060 Rev Page ADM1060 Arbitrator µF capacitor is DD ...
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... ADM1060ARU–REEL7 –40°C to +85°C 1 EVAL–ADM1060EB 1 Contact factory for availability of the evaluation board. For general ADM1060 support, send email to: Figure 39. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters Package Description 28-lead TSSOP 28-lead TSSOP ...
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... NOTES Rev Page ADM1060 ...
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... ADM1060 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03470–0–12/03(B) Rev Page ...