ADM1062 Analog Devices, ADM1062 Datasheet
ADM1062
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ADM1062 Summary of contents
Page 1
... The ADM1062 Super Sequencer® configurable supervisory/ sequencing device that offers a single-chip solution for supply monitoring and sequencing in multiple-supply systems. In addition to these functions, the ADM1062 integrates a 12-bit ADC and six 8-bit voltage output DACs. These circuits can be used to implement a closed-loop margining system that enables supply adjustment by altering either the feedback node or the reference of a dc-to-dc converter using the DAC outputs ...
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... Choosing the Size of the Attenuation Resistor....................... 23 DAC Limiting and Other Safety Features ............................... 23 Temperature Measurement System.............................................. 24 Remote Temperature Measurement ........................................ 24 Applications Diagram .................................................................... 26 Communicating with the ADM1062........................................... 27 Configuration Download at Power-Up................................... 27 Updating the Configuration ..................................................... 27 Updating the Sequencing Engine............................................. 28 Internal Registers........................................................................ 28 ...
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... Change to Figure 3 ............................................................................9 Added Exposed Pad Notation to Outline Dimensions ..............34 Changes to Ordering Guide...........................................................35 5/08—Rev Rev. B Changes to Table 1 ............................................................................4 Changes to Powering the ADM1062 Section ..............................13 Changes to Table 5 ..........................................................................14 Changes to Sequence Detector Section ........................................18 Changes to Temperature Measurement System Section ............23 Changes to Table 11 ........................................................................24 Changes to Configuration Download at Power-Up Section .....26 Changes to Table 12 ...
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... This design enables very flexible sequencing of the outputs, based on the condition of the inputs. The ADM1062 is controlled via configuration data that can be programmed into an EEPROM. The entire configuration can be programmed using an intuitive GUI-based software package provided by Analog Devices, Inc. ...
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... The ADC can convert signals presented to the VH, VPx, and VXx pins; VPx and VH input signals are attenuated depending on the selected range; a signal at the pin corresponding to the selected range is from 0.573 V to 1.375 V at the ADC input Endpoint corrected 2.048 V REFIN V = 2.048 V REFIN ADM1062 ...
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... ADM1062 Parameter Conversion Time Offset Error Input Noise 2 TEMPERATURE SENSOR Local Sensor Accuracy Local Sensor Supply Voltage Coefficient Remote Sensor Accuracy Remote Sensor Supply Voltage Coefficient Remote Sensor Current Source Temperature for Code 0x800 Temperature for Code 0xC00 Temperature Resolution per Code ...
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... IN 1 μ μA VDDCAP = 4. 2.0 V 0 OUT 400 kHz 1.3 μs 0.6 μs 0.6 μs 0.6 μs 1.3 μs 0.6 μs 300 ns 300 ns 100 μ μs Rev Page ADM1062 = 25°C if known logic state is required A = −3 ...
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... ADM1062 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Voltage on VH Pin Voltage on VPx Pins Voltage on VXx Pins Voltage on A0, A1 Pins Voltage on REFIN, REFOUT Pins Voltage on VDDCAP, VCCP Pins Voltage on PDOx Pins Voltage on SDA, SCL Pins Voltage on GND, AGND, PDOGND, REFGND Pins Voltage on DN, DP Pins ...
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... INDICATOR VX2 3 VX3 4 VX4 5 ADM1062 VX5 6 TOP VIEW VP1 7 (Not to Scale) VP2 8 VP3 9 VP4 CONNECT Figure 4. TQFP Pin Configuration ADM1062 NC 36 PDO1 35 PDO2 34 PDO3 33 PDO4 32 PDO5 31 PDO6 30 PDO7 29 PDO8 28 PDO9 27 PDO10 ...
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... ADM1062 Pin No. 1 Mnemonic LFCSP TQFP 39 46 VDDCAP GND 1 Note that the LFCSP has an exposed pad on the bottom. This pad connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability typical application, all ground pins are connected together. ...
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... VP1 Figure 8. I vs. V (VP1 Not as Supply) VP1 VP1 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 (V) VH Figure 9. I vs. V (VH as Supply 350 300 250 200 150 100 (V) VH Figure 10. I vs. V (VH Not as Supply ADM1062 ...
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... ADM1062 2.5 5.0 7.5 I (µA) LOAD Figure 11. Charge-Pumped V (FET Drive Mode) vs. I PDO1 5.0 4.5 4.0 3.5 3.0 2.5 VP1 = 3V 2.0 1.5 1.0 0 (mA) LOAD Figure 12. V (Strong Pull-Up to VPx) vs. I PDO1 4.5 4.0 3.5 VP1 = 5V 3.0 2.5 VP1 = 3V 2.0 1.5 1.0 0 (µA) LOAD Figure 13. V (Weak Pull-Up to VPx) vs. I PDO1 10 ...
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... VP1 = 4.75V 0.999 0.998 0.997 0.996 0.995 –40 – TEMPERATURE (°C) Figure 19. DAC Output vs. Temperature 2.058 2.053 VP1 = 3.0V 2.048 VP1 = 4.75V 2.043 2.038 –40 – TEMPERATURE (°C) Figure 20. REFOUT vs. Temperature ADM1062 VP1 = 3.0V 80 100 80 100 ...
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... The VH input pin can accommodate supplies up to 14.4 V, which allows the ADM1062 to be powered using backplane supply. In cases where this 12 V supply is hot swapped recommended that the ADM1062 not be connected directly to the supply. Suitable ...
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... Table 6 shows the details of each input. PROGRAMMING THE SUPPLY FAULT DETECTORS The ADM1062 can have SFDs on its 10 input channels. These highly programmable reset generators enable the supervision supply voltages. The supplies can be as low as 0.573 V and as high as 14 ...
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... VXx input pins on the ADM1062 have dual functionality. The second function digital logic input to the device. Therefore, the ADM1062 can be configured for up to five digital inputs. These inputs are TTL-/CMOS-compatible. Standard logic signals can be applied to the pins: RESET from reset generators, PWRGD signals, fault flags, manual resets, and so on ...
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... Because of this, the PDOx pins are pulled to GND by a weak (20 kΩ) on-chip pull-down resistor. As the input supply to the ADM1062 ramps up on VPx or VH, all the PDOx pins behave as follows: Input supply = 1.2 V. The PDOs are high impedance. ...
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... If VP2 is not okay State DIS3V3. PWRGD If VX1 is high State DIS2V5. MONITOR FAULT The ADM1062 offers state definitions. The signals monitored to indicate the status of the input pins are the outputs of the SFDs. WARNINGS The SE also monitors warnings. These warnings can be generated when the ADC readings violate their limit register value or when the secondary voltage monitors on VPx and VH are triggered ...
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... STATES EN3V3 10ms VP1 = 0 VP2 = 1 EN2V5 DIS3V3 20ms (VP1 + VP2 VX1 = 1 VP3 = 1 PWRGD DIS2V5 VP2 = 0 (VP1 + VP2 + VP3 VX1 = 1 VX1 = 1 FSEL1 (VP1 + VP2 VP3 = 0 FSEL2 VP2 = 0 Figure 28. Sample Application Flow Diagram DIS2V5 PWRGD FSEL1 ADM1062 FSEL2 ...
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... This ensures that only real faults are captured and not, for example, undervoltage conditions that may be present during a power-up or power-down sequence. The ADM1062 also has a number of status registers. These include more detailed information, such as whether an undervoltage or FAULT overvoltage fault is present on a particular input. The status regis- ters also include information on ADC limit faults ...
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... The maximum setting for the REFIN pin is 2.048 V. SUPPLY SUPERVISION WITH THE ADC In addition to the readback capability, another level of supervi- sion is provided by the on-chip, 12-bit ADC. The ADM1062 has limit registers with which the user can program a maximum or minimum allowable threshold. Exceeding the threshold generates DIGITIZED ...
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... Figure 33). The voltage on the rail to be margined can be read back to accurately margin the rail to the target voltage. The ADM1062 incorporates all the circuits required to do this, with the 12-bit successive approximation ADC used to read back the level of the supervised voltages, and the six voltage output DACs, implemented as described in the Open-Loop Supply Margining section, used to adjust supply levels ...
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... PCB GND TRACE NOISE DECOUPLING CAPACITOR Figure 33. Closed-Loop Margining System Using the ADM1062 the current flowing through R3. Therefore, a direct relationship exists between the extra voltage drop across R1 during margining and the voltage drop across R3. This relationship is given by the following equation: ΔV where: Δ ...
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... DN input, and the emitter is connected to the DP input NPN transistor is used, the emitter is connected to the DN input, and the base is connected to the DP input. Figure 34 and Figure 35 show how to connect the ADM1062 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, ...
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... BE −75°C −50°C −25°C −10°C 0°C +10.25°C +25.5°C +50.75°C +75°C +100°C +125°C +128°C Rev Page ADM1062 Digital Output (Hex) Digital Output (Binary) 0x400 010000000000 0x418 010000011000 0x4E0 010011100000 0x5A8 010110101000 0x670 011001110000 0x738 011100111000 ...
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... OUT 3.3V OUT 2.5V OUT 1.8V OUT 1.2V OUT 0.9V OUT POWRON RESET *ONLY ONE MARGINING CIRCUIT SHOWN FOR CLARITY. DAC1 TO DAC6 ALLOW MARGINING FOR UP TO SIX VOLTAGE RAILS. 3.3V OUT 2.5V OUT VH ADM1062 VP1 PDO1 VP2 PDO2 VP3 VP4 VX1 PDO3 VX2 PDO4 VX3 PDO5 PWRGD PDO6 ...
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... EEPROM contents to the RAM again, as described in Option 3, restoring the ADM1062 to its original configuration. The topology of the ADM1062 makes this type of operation possible ...
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... Therefore, access to the ADM1062 is restricted until the download is complete. Identifying the ADM1062 on the SMBus The ADM1062 has a 7-bit serial bus slave address (see Table 12). The device is powered up with a default serial bus address. The five MSBs of the address are set to 00101; the two LSBs are determined by the logical states of Pin A1 and Pin A0 ...
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... SLAVE FRAME 1 COMMAND CODE ACK. BY SLAVE FRAME 3 DATA BYTE Figure 39. General SMBus Write Timing Diagram Rev Page ACK. BY SLAVE FRAME STOP ACK SLAVE FRAME N MASTER DATA BYTE ADM1062 ...
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... ADM1062 1 SCL SDA START BY MASTER SLAVE ADDRESS 1 SCL (CONTINUED) SDA D7 D6 (CONTINUED) t SCL HD; STA SDA t BUF R ACK. BY SLAVE FRAME ACK. BY MASTER FRAME 3 DATA BYTE Figure 40. General SMBus Read Timing Diagram ...
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... The slave asserts an ACK on SDA. 6. The master asserts a stop condition on SDA, and the transaction ends. In the ADM1062, the send byte protocol is used for two purposes: To write a register address to the RAM for a subsequent single byte read from the same address, or for a block read or a block write starting at that address, as shown in Figure 42 ...
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... The master asserts a NACK on SDA. 6. The master asserts a stop condition on SDA, and the transaction ends. In the ADM1062, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation, as shown in Figure 48. ...
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... EEPROM, a block write to the RAM/EEPROM block read from the RAM/ EEPROM. This option enables the user to verify that the data received by or sent from the ADM1062 is correct. The PEC byte is an optional byte sent after the last data byte has been written to or read from the ADM1062 ...
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... ADM1062 OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 1.05 1.00 0.95 0.15 0.05 ROTATED 90° CCW 6.00 BSC SQ 0.60 MAX 0.50 TOP BSC 5.75 VIEW BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 COPLANARITY 0.20 REF 0.23 0.08 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad ...
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... Temperature Range ADM1062ACPZ −40°C to +85°C ADM1062ACPZ-REEL7 −40°C to +85°C ADM1062ASUZ −40°C to +85°C ADM1062ASUZ-REEL7 −40°C to +85°C EVAL-ADM1062TQEBZ RoHS Compliant Part. Package Description 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 48-Lead TQFP 48-Lead TQFP Evaluation Kit (TQFP Version) Rev ...
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... ADM1062 NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04433-0-6/11(C) Rev Page ...