CS8420-DSZ Cirrus Logic Inc, CS8420-DSZ Datasheet
CS8420-DSZ
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CS8420-DSZ Summary of contents
Page 1
... H/S RST http://www.cirrus.com General Description The CS8420 is a stereo digital audio sample rate con- verter (SRC) with AES3-type and serial digital audio inputs, AES3-type and serial digital audio outputs, and includes comprehensive control ability via a 4-wire mi- crocontroller port. Channel status and user data can be assembled read/modify/write cycles easy ...
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... Serial Audio Output Port Data Format (06h) ................................................................................ 39 10.8 Interrupt 1 Register Status (07h) (Read Only) ............................................................................. 40 10.9 Interrupt Register 2 Status (08h) (Read Only) ............................................................................. 41 10.10 Interrupt 1 Register Mask (09h) ................................................................................................. 41 10.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh) ..................................................... 41 10.12 Interrupt 2 Register Mask (0Ch) ................................................................................................. 42 2 CS8420 DS245F4 ...
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... User Data Buffer Control (13h) .................................................................................................. 46 10.19 Sample Rate Ratio (1Eh) (Read Only) ....................................................................................... 47 10.20 C-Bit or U-Bit Data Buffer (20h - 37h) ........................................................................................ 47 10.21 CS8420 I.D. and Version Register (7Fh) (Read Only) ............................................................... 47 11. SYSTEM AND APPLICATIONS ISSUES ........................................................................................... 48 11.1 Reset, Power Down and Start-up Options ................................................................................... 48 11 ...
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... Figure 4.I²C Mode Timing ......................................................................................................................... 11 Figure 5.Recommended Connection Diagram for Software Mode ........................................................... 12 Figure 6.Software Mode Audio Data Flow Switching Options ................................................................... 14 Figure 7.CS8420 Clock Routing ................................................................................................................ 14 Figure 8.Serial Audio Input, using PLL, SRC Enabled .............................................................................. 16 Figure 9.Serial Audio Input, No PLL, SRC Enabled .................................................................................. 16 Figure 10.AES3 Input, SRC Enabled ........................................................................................................ 16 Figure 11 ...
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... Figure 44.Revision D Jitter Attenuation ..................................................................................................... 90 Figure 45.Revision D1 Jitter Attenuation ................................................................................................... 90 LIST OF TABLES Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN ...................... 28 Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK ........................... 28 Table 3. Non-SRC Delay ........................................................................................................................... 29 Table 4. Summary of all Bits in the Control Register Map ........................................................................ 33 Table 5 ...
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... Ambient Operating Temperature (power applied) Storage Temperature Notes: 1. Transient currents 100 mA will not cause SCR latch-up. 6 Symbol Min VD+, VA+ 4.75 Commercial Grade T A Automotive Grade Symbol VD+, VA+ (Note stg CS8420 Typ Max Units 5.0 5.25 V -10 - +70 °C -40 - +85 °C Min Max Units - 6 ± ...
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... Power Down Mode is defined as RST = LO with all clocks and data lines held static. 4. Normal operation is defined as RST = HI. DS245F4 Symbol (serial input port) Fsi Fso THD+N Symbol Upsampling Downsampling 0.5465*Fso (Note Δt gd Symbol VA+ VD+ VA+ si VD+ VA+ si VD+ CS8420 Min Typ Max Units 120 128 - 8 - 108 kHz 8 - 108 kHz 0. -117 - - -112 - ...
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... PLL is bypassed (RXD1:0 bits in the Clock Source Control register set to 10b), clock is input to the RMCK pin. 8 Symbol Symbol Symbol R TXP R TXN = 20 pF. L Symbol (Note 5) (Note 6) (Note 6) CS8420 Min Typ Max Units μA - ±10 ±15 200 - - mVpp Min Max Units (VD 0.4 V (VD ...
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... ILRCK OLRCK (input) t lrckd ISCLK OSCLK (input SDIN SDOUT Figure 2. Audio Port Slave Mode and Data Input Timing CS8420 Min Typ Max Units - - ...
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... Data must be held for sufficient time to bridge the transition time of CCLK. 15. For f < 1 MHz. sck CS t css CCLK CDIN CDOUT pF. L Symbol (Note 13) f sck t csh t css t scl t sch t dsu (Note 14 (Note 15 (Note 15 scl t sch dsu Figure 3. SPI Mode Timing CS8420 Min Typ Max Units 0 - 6.0 MHz μs 1 100 ns ...
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... L Symbol fscl t buf t hdst t low t high t sust (Note 16) t hdd t sud susp Repeated Start t high t t sud t sust hdd Figure 4. I²C Mode Timing CS8420 ® MODE Min Typ Max Units - - 100 kHz μs 4 μs 4 μs 4 μs 4 μs 4 μs 0 ...
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... CS8420 ILRCK OLRCK ISCLK OSCLK SDIN SDOUT RMCK SDA/CDOUT OMCK AD0 / CS SCL/CCLK AD1/CDIN INT EMPH / AD2 U RERR RST TCBL H/S AGND FILT DGND RFILT CFILT CRIP CS8420 +5V Digital Supply AES3/ Cable SPDIF Interface Equipment 3-wire Serial Audio Input Device Microcontroller DS245F4 ...
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... The CS8420 is intended for 16-, 20-, and 24-bit applications where the input sample rate is unknown known to be asynchronous to the system sample rate. On the input side of the CS8420, AES3 or 3-wire serial format can be chosen. The output side produces both AES3 and 3-wire serial format. An I²C/SPI-compatible microcontroller interface allows full block processing of channel sta- tus and user data via block reads from the incoming AES3 data stream and block writes to the outgoing AES3 data stream ...
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... DATA I/O FLOW AND CLOCKING OPTIONS The CS8420 can be configured for nine connectivity alternatives, referred to as data flows. Each data flow has an associated clocking set-up. Figure 6 the switches. This drawing only shows the audio data paths for simplicity. and the associated control register bits. The clock routing constraints determine which data routing options are ac- tually usable ...
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... By studying the following drawings, and appropriately setting the Data Flow Control and Clock Source Control reg- ister bits, the CS8420 can be configured to fit a variety of application requirements. The following drawings illustrate the possible valid data flows. The audio data flow is indicated by the thin lines; the clock routing is indicated by the bold lines ...
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... Figure 11. Serial Audio Input, AES3 Input Clock Source, Serial OLRCK Audio OSCLK Output SDOUT RXN TXP RXP TXN RMCK Figure 13. AES3 Input, SRC to Serial Audio Output, Serial CS8420 Serial OLRCK Audio OSCLK Output SDOUT Serial Sample Audio Rate Input Converter TXP AES3 Encoder & ...
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... AES3 TXP Encoder & Driver TXN Data Flow Control Bits Figure 15. AES3 Input to Serial Audio Output Only TXP AES3 Encoder & Driver TXN CS8420 AES3 Serial Rx & Audio Decode Output PLL RMCK Clock Source Control Bits TXD1-0: 10 OUTC: 1 SPD1-0: 10 INC: 0 SRCD: ...
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... When using the AES3 input, and when using the serial audio input port in Left-Justified and I²S modes, all input data is treated as 24 bits wide. Any truncation that has been done prior to the CS8420 to less than 24 bits should have been done using an appropriate dither process. If the serial audio input port is used to feed the SRC, and the port is in Right-Justified mode, then the input data will be truncated to the SIRES bit setting value ...
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... Figure 17 shows a selection of common input formats, along with the control bit settings. The clocking of the input section of the CS8420 may be derived from the incoming ILRCK word rate clock, using the on-chip PLL. The PLL operation is described in the AES receiver description on the PLL locks onto the leading edges of the ILRCK clock. ...
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... See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit 20 Channel A LSB MSB Channel A LSB MSB Channel A MSB LSB SISF SIRES1/0 SIJUST 00 XX* 1 Figure 17. Serial Audio Input Example Formats CS8420 Channel B LSB MSB Channel B LSB MSB Channel B MSB LSB SIDEL SISPOL SILRPOL DS245F4 ...
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... DS245F4 Channel A LSB MSB Channel A LSB Channel A MSB LSB Channel B LSB LSB MSB MSB Frame 0 SOSF SORES1/0 SOJUST CS8420 Channel B LSB Channel B MSB LSB Channel B MSB Extended MSB Channel A Channel B LSB MSB MSB V SODEL SOSPOL SOLRPOL MSB MSB LSB ...
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... Error Reporting and Hold Function While decoding the incoming AES3 data stream, the CS8420 can identify several kinds of error, indicated in the Receiver Error register. The UNLOCK bit indicates whether the PLL is locked to the incoming AES3 data. The V bit reflects the current validity bit status. The CONF (confidence) bit indicates the amplitude of the eye pattern opening, indicating a link that is close to generating errors ...
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... If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required transitions are aligned within 1% of VLRCK period to VLRCK edges Figure 19. AES3 Receiver Timing for C & U Pin Output Data DS245F4 describes the overall handling of CS and “Channel Status and User Data Buffer Management” on page 81 ± CS8420 de- 23 ...
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... MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8420 AES3 receiver can detect such non-audio data. This is accomplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the sync code is detected, an internal AUTODETECT signal will be asserted ...
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... The line drivers are low-skew, low-impedance, differential outputs capable of driving cables directly. Both drivers are set to ground during reset (RST = low), when no AES3 transmit clock is provided, and option- ally under the control of a register bit. The CS8420 also allows immediate mute of the AES3 transmitter audio data via a control register bit. ...
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... Data [2]* Y Data [3]* AES3 Transmitter in Mono Mode . VCU[3] VCU[4] Data [8] Data [3] X Data [4] Tsetup = > 7.5 % AES3 frame time Thold = 0 Tth > 3 OMCK if TCBL is Input U[2] Data [8] X Data [4]* X Data [5]* Tsetup = > AES3 frame time Thold = 0 Tth > 3 OMCK if TCBL is Input CS8420 DS245F4 ...
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... A & B sub-fames SRC Aout SRC Bout B2 Outgoing AES3 A1 A2 Outgoing B2 B1 AES3 A selected Outgoing A2 B2 AES3 B selected CS8420 TRANSMITTER STEREO MODE 96kHz stereo 96kHz frame rate A AES3 B Transmitter OMCK (256, 384, or 512x 96kHz) TRANSMITTER MONO MODE 96kHz mono 48kHz frame rate A + AES3 B ...
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... To start the parts simultaneously, set up each one so that the PLL will lock, with the active input port driving both output ports. Then simultaneously enable the RUN bits in all of the parts. TCBL on one of the CS8420 parts should be set as an output, while the remaining TCBL pins should be set as inputs. This synchronizes the AES transmitter on all of the parts ...
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... The inputs and outputs are synchronous to one another. Serial Input Serial Output Serial Input to Serial Output DS245F4 . The AES receiver has a interface delay of two s Path Delay (in units of a frame ± 1/128 2 ± 1/128 3 ± 1/128 2 ± 1/128 Table 3. Non-SRC Delay CS8420 29 ...
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... The control port has two modes: SPI and I²C, with the CS8420 acting as a slave device. SPI mode is selected if there is a high-to-low transition on the AD0/CS pin after the RST pin has been brought high. I²C mode is selected by connecting the AD0/CS pin to VD+ or DGND, thereby permanently selecting the desired AD0 bit address state ...
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... VD+ or DGND as desired. The EMPH pin is used to set the AD2 bit, by connecting a resistor from the EMPH pin to VD DGND. The state of the pin is sensed while the CS8420 is being reset. The upper four bits of the 7-bit address field are fixed at 0010b. To communicate with a CS8420, the chip address field, which is the first byte sent to the CS8420, should match 0010b followed by the settings of the EMPH, AD1, and AD0 ...
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... Reserved C-bit or U-bit Data Buffer 56 to 126 - Reserved 127 - Chip ID and version register Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8420 MAP4 MAP3 CS8420 ...
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... AUX1 AUX0 0 QCRC CCRC UNLOCK 0 QCRCM CCRCM UNLOCKM 0 0 BSEL CBMR SRR7 SRR6 SRR5 SRR4 ID3 ID2 ID1 ID0 CS8420 DITH INT1 INT0 TCBLD MMR MMT MMTCS MMTLR TXD0 SPD1 SPD0 SRCD OUTC INC RXD1 RXD0 SIJUST SIDEL SISPOL SILRPOL SOJUST ...
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... Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. This setting requires an external pull up resistor on the INT pin Reserved TCBLD Transmit Channel Status Block pin (TCBL) direction specifier 0 - TCBL is an input (default TCBL is an output MUTEAES DITH CS8420 INT1 INT0 TCBLD DS245F4 ...
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... CS data. If MMTLR = 1, use the right channel CS data. MMTLR Channel Selection for AES Transmitter mono mode 0 - Use left channel input data for consecutive sub-frame outputs (default Use right channel input data for consecutive sub-frame outputs DS245F4 RMCKF MMR CS8420 MMT MMTCS MMTLR 35 ...
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... Serial audio input port 10 - AES3 receiver 11 - Reserved SPD[1:0] Serial Audio Output Port Data Source 00 - SRC output (default Serial Audio Input Port 10 - AES3 receiver 11 - Reserved SRCD Input Data Source for SRC 0 - Serial Audio Input Port (default AES3 Receiver TXD1 TXD0 CS8420 SPD1 SPD0 SRCD DS245F4 ...
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... Reading and writing the U and C data buffers is not possible. Power consumption is low (default Normal part operation. This bit must be written to the 1 state to allow the CS8420 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1 ...
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... SDIN sampled on rising edges of ISCLK (default SDIN sampled on falling edges of ISCLK SILRPOL ILRCK clock polarity 0 - SDIN data is for the left channel when ILRCK is high (default SDIN data is for the right channel when ILRCK is high SIRES0 SIJUST CS8420 SIDEL SISPOL SILRPOL DS245F4 ...
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... SDOUT transitions occur on falling edges of OSCLK (default SDOUT transitions occur on rising edges of OSCLK SOLRPOL OLRCK clock polarity 0 - SDOUT data is for the left channel when OLRCK is high (default SDOUT data is for the right channel when OLRCK is high DS245F4 SORES0 SOJUST CS8420 SODEL SOSPOL SOLRPOL 39 ...
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... Sample rate range exceeded indicator. Occurs if Fsi/Fso or Fso/Fsi exceeds 3. OVRGL Over-range indicator for left (A) channel SRC output. Occurs on internal over-range for left channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale. OVRGR Over-range indicator for right (B) channel SRC output. Occurs on internal over-range for right channel data ...
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... These registers default to 00 Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved DS245F4 REUNLOCK DETU OVRGLM OVRGRM OVRGL1 OVRGR1 OVRGL0 OVRGR0 CS8420 EFTU QCH UOVW DETCM EFTCM RERRM DETC1 EFTC1 RERR1 DETC0 EFTC0 RERR0 41 ...
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... INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt condition the continuing occurrence of the interrupt condition. These registers default to 00 Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved REUNLOCKM DETUM REUNLOCK1 DETU1 REUNLOCK0 DETU0 CS8420 EFTUM QCHM UOVWM EFTU1 QCH1 UOVW1 EFTU0 QCH0 UOVW0 DS245F4 ...
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... SCMS generation indicator. This is decoded from the category code and the L bit Received data is 1st generation or higher 1 - Received data is original Note: COPY and ORIG will both be set the incoming data is flagged as professional or if the receiver is not in use. DS245F4 AUX0 PRO CS8420 AUDIO COPY ORIG 43 ...
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... BIP Bi-phase error bit. Updated on sub-frame boundaries error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR Parity bit. Updated on sub-frame boundaries error 1 - Parity error UNLOCK V CS8420 CONF BIP PAR DS245F4 ...
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... CAM is set to 0 (One Byte Mode Channel B information is displayed at the EMPH pin and in the receiver channel status register. Channel B information is output during control port reads when CAM is set to 0 (One Byte Mode) DS245F4 UNLOCKM CBMR DETCI CS8420 CONFM BIPM PARM EFTCI CAM CHS 45 ...
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... Q[7]. Similarly bit 0 of address 1Dh corresponds to Q[79 UBM1 CONTROL ADDRESS TRACK TRACK INDEX INDEX MINUTE MINUTE SECOND SECOND FRAME FRAME ZERO ZERO ABS FRAME ABS FRAME CS8420 UBM0 DETUI EFTUI ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK INDEX INDEX INDEX MINUTE MINUTE MINUTE SECOND SECOND SECOND FRAME FRAME ...
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... The fractional part of the sample rate ratio 10.20 C-Bit or U-Bit Data Buffer (20h - 37h) Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is ac- cessible via these register addresses. 10.21 CS8420 I.D. and Version Register (7Fh) (Read Only ID3 ...
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... The pins are then switched to be outputs. This mechanism allows output pins to be used to set alternative modes in the CS8420 by connecting a 47 kΩ resistor between the pin and either VD+ (High) or DGND (Low). For each mode, every start-up option select pin MUST have an external pull-up or pull-down resistor. In software mode, the only start-up option pin is EMPH, which is used to set a chip ad- dress bit for the control port in I² ...
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... SRC Invalid State Occasionally the CS8420 SRC will enter an invalid state. This can happen after the RUN bit has been set when an AES3 stream is first plugged into the part or when a source device interrupts the SRC input stream. When this happens, two symptoms may be noticeable: notches occurring in the frequency response and spurious tones being generated in response to some input frequencies ...
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... ID Code and Revision Code The CS8420 has a register that contains a 4-bit code to indicate that the addressed device is a CS8420. This is useful when other CS84xx family members are resident in the same system, allowing common soft- ware modules. ...
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... OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x, 384x, or 512x the output sample rate (Fso). RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will frequency of 128x or 256x the input sample rate (Fsi). DS245F4 CS8420 51 ...
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... INT - Interrupt Output The INT output pin indicates errors and key events during the operation of the CS8420. All bits affecting INT are maskable via control registers. The condition(s) that initiated interrupt are readable via a control register. The polarity of the INT output, as well as selection of a standard or open-drain output, is set via a control register. Once set true, the INT pin goes false only after the interrupt status registers have been read, and the interrupt status bits have re- turned to zero ...
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... AD0/CS - Address Bit 0 (I²C) / Control Port Chip Select (SPI) A falling edge on this pin puts the CS8420 into SPI Control Port mode. With no falling edge, the CS8420 defaults to I²C mode. In I²C mode, AD0 is a chip address pin. In SPI mode used to enable the control port interface on the CS8420. AD1/CDIN - Address Bit 1 (I² ...
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... The U pin should not be tied directly to ground in case it is programmed output and subsequently tries to output a logic high. This situation may affect the long-term reliability of the device. If the U pin is driven by a logic level output, a 100 Ω series resistor is recommended. 54 CS8420 Figure 20 for Figure 19 ...
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... The CS8420 has six Hardware modes, which allow use of the device without using a micro-controller to ac- cess the device control registers and CS & U data. The flexibility of the CS8420 is necessarily limited in Hardware mode. Various pins change function in Hardware mode, and various data paths are also possible. ...
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... Mode 1B: CUV transmitted data is input serially on pins, received PRO, EMPH, AUDIO are not visible Serial Output Format OF1 Serial Output Format OF2 Serial Output Format OF3 Serial Output Format OF4 Table 8. Hardware Mode 1 Start-Up Options CS8420 Output Clock Source OMCK OLRCK Serial ...
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... Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will frequency of 256x the input sample rate (Fsi). This is also a start-up option pin and requires a pull-up or pull-down resistor. DS245F4 CS8420 57 ...
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... TCBLD - Transmit Channel Status Block Direction Input Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input. TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. 58 ...
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... VD+ VD+ DFC1 S/AES H/S Clocked by Clocked by Input Derived Clock Output Clock Sample Rate Converter C & U bit Data Buffer SFMT1 SFMT0 COPY/C ORIG/U EMPH/V CUVEN TCBL CS8420 7 and 10. Output Clock Source OMCK OLRCK Serial Audio OSCLK Output SDOUT AES3 TXP Encoder TXN & ...
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... Serial Input & Output Format IF2&OF2 0 Serial Input & Output Format IF3&OF3 Serial Input & Output Format IF4&OF3 1 LOCK Function - Serial Output Port is Slave - Serial Output Port is Master LO TCBL is an input HI TCBL is an output Table 11. Hardware Mode 2 Start-Up Options CS8420 DS245F4 ...
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... Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi) DS245F4 CS8420 Table 10. 61 ...
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... Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times ...
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... VD+ OSCLK DFC1 H/S SDOUT OLRCK ILRCK Serial Clocked by Audio Output Clock Output Sample Rate Converter C & U bit Data Buffer COPY ORIG EMPH/U AUDIO/V TCBL PRO/C CS8420 Output Clock Source ISCLK SDIN OMCK Serial Audio Input AES3 TXP Encoder TXN & ...
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... EMPH and AUDIO is not visible Serial Input & Output Format IF1&OF1 Serial Input & Output Format IF2&OF2 Serial Input & Output Format IF3&OF3 Serial Input & Output Format IF2&OF4 TCBL is an input TCBL is an output Table 12. Hardware Mode 3 Start-Up Options CS8420 Function DS245F4 ...
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... SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. DS245F4 CS8420 Table 5. 65 ...
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... Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times ...
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... VD+ OSCLK DFC1 H/S SDOUT OLRCK ILRCK Serial Audio Output C & U bit Data Buffer PRO/C COPY ORIG EMPH/U AUDIO/V TCBL CS8420 ISCLK SDIN Serial APMS Audio Input AES3 TXP Encoder TXN & ...
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... EMPH and AUDIO is not visible - Serial Input & Output Format IF1&OF1 - Serial Input & Output Format IF2&OF2 - Serial Input & Output Format IF3&OF3 - Serial Input & Output Format IF1&OF5 - TCBL is an input - TCBL is an output Table 13. Hardware Mode 4 Start-Up Options CS8420 Function DS245F4 ...
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... APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the port as a slave. Audio Output Interface: SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. DS245F4 CS8420 Table 5. 69 ...
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... Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times ...
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... Serial Output Port is Master LO LO Serial Output Format OF1 LO HI Serial Output Format OF2 HI LO Serial Output Format OF3 HI HI Serial Output Format OF5 Table 14. Hardware Mode 5 Start-Up Options CS8420 OMCK OLRCK Serial Audio OSCLK Output SDOUT C U RCBL Function 71 ...
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... OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi). 72 CS8420 Table 5. DS245F4 ...
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... A is selected when CHS is low, channel B is selected when CHS is high User Data Output The U pin outputs user data from the AES3 receiver, clocked by rising and falling edges of OLRCK Channel Status Data Output The C pin outputs channel status data from the AES3 receiver, clocked by rising and falling edges of OLRCK. DS245F4 CS8420 73 ...
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... Audio data is input via the serial audio input port and shows the timing requirements. VD+ VD+ VD+ S/AES H/S FILT DFC1 Data Buffer SFMT1 SFMT0 COPY/C ORIG EMPH AUDIO TCBL CS8420 Table 15 shows how the COPY/C and Table 15, and may be set to master or Output Clock Source OMCK AES3 TXP Encoder TXN & ...
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... Function 0 PRO=0, COPY=0, L=0 1 PRO=0, COPY=0, L=1 0 PRO=0, COPY=1, L=0 1 PRO=1 Table 15 COPY/C and ORIG Pin Function SFMT0 Function 0 Serial Input Format IF1 1 Serial Input Format IF2 0 Serial Input Format IF3 Serial Input Format IF4 1 Table 16 Serial Port Format Selection CS8420 75 ...
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... Data Input Audio data serial input pin. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin *24 VA+ 6* * RST Table CS8420 ORIG DFC1 TXP TXN H/S VD+ DGND OMCK S/AES AUDIO U V CEN TCBL Table 15. DS245F4 5. ...
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... AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times ...
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... AES3 Transmitter External Components The output drivers on the CS8420 are designed to drive both the professional and consumer interfaces. The AES3 specification for professional/broadcast use calls for a 110 Ω source impedance and a balanced drive capability. Since the transmitter output impedance is very low, a 110 Ω resistor should be placed in series with one of the transmit pins. The specifications call for a balanced output drive of 2-7 volts peak-to-peak into a 110 Ω ...
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... AES3 Receiver External Components The CS8420 AES3 receiver is designed to accept both the professional and consumer interfaces. The dig- ital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110 Ω ±20% impedance. The XLR connector on the receiver should have female pins with a male shell. Since the receiver has a very high input impedance, a 110 Ω ...
Page 80
... Coax The circuit shown in Figure 36 TTL/CMOS logic outputs drive the CS8420 receiver section. 14.3 Isolating Transformer Requirements The transformer should be capable of operating from 1 MHz, which is equivalent to an audio data rate of 25 kHz to 108 kHz after bi-phase mark encoding. Transformers provide isolation from ground loops noise, and common mode noise and interference ...
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... AES3 Channel Status(C) Bit Management The CS8420 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these RAMs via the control port. ...
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... E buffer actually gets transmitted and not overwritten by a D-to-E transfer. If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calcu- lated by the CS8420, and does not have to be written into the last byte of the block by the host microcon- troller. ...
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... In this case, the user would have to superimpose his settings on the E buffer after every D-to-E overwrite. To avoid this problem, the CS8420 has the capability of reserving the first 5 bytes of the E buffer for user writes only. When this capability is in use, internal D-to-E buffer transfers will NOT affect the first 5 bytes of the E buffer ...
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... In these situations, Two-Byte mode should be used to access the E buffer. In this mode, a read will cause the CS8420 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be input to the CS8420's control port ...
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... Storing only IUs (and not filler) within the FIFO makes it possible for the slower AES3 transmitter to “catch up” to the faster AES3 receiver as data is read out of the FIFO. This is because nothing is written into the FIFO when long strings of zeros are input to the AES-EBU receiver. During this time of no writing, the DS245F4 CS8420 85 ...
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... Example 1: Fsi/Fso = 2, N=4, IF=1: minimum proper padding is 53 bits. Example 2: Fsi/Fso = 1, N=4, IF=7: min proper padding is 9 bits. The CS8420 detects when an overwrite has occurred in the FIFO, and synchronously resets the entire FIFO structure to prevent corrupted U data from being merged into the transmitted AES3 data stream. ...
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... An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure simplified diagram of the PLL in CS8420 devices. When the PLL is locked to an AES3 input stream updated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, F ...
Page 88
... Revision FILT and the other three capacitors are in an 0805 FILT 1000 Crip pF Cfilt .1µF Figure 42. Recommended Layout Example Pre-October 2002 (10-Digit) Zxxxxxxxxx Rxxxxxxxxx Table 17. Second Line Part Marking CS8420 , an X7R dielectric is preferred. Avoid ca- New (12-Digit) ZFBADXxxxxxx RFBAD1xxxxxx DS245F4 ...
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... Also note that many factors can affect jitter performance in a system. Please follow the circuit and layout recommendations outlined previously. 16.3.3 Locking to the ILRCK Input CS8420 parts that are configured to lock to the ILRCK input should use the external PLL component val- ues listed in Table 20 ...
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... Jitter Tolerance Shown in Figure 43 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4 specification. CS8420 parts used with the appropriate external PLL component values (as noted in Table 19) have been tested to pass this template. 16.3.5 Jitter Attenuation Shown in Figure 44 and ...
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... AES3 Transmitter Output Jitter With a jitter free OMCK clock, what is the jitter added by the AES3 transmitter. Gain Error The difference in amplitude between the output and the input signal level, within the passband of the digital filter in the SRC. DS245F4 CS8420 91 ...
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... Symbol θ CS8420 MILLIMETERS MAX 2.65 0.30 0.51 0.32 18.10 7.60 1.52 10.65 1.27 8° Min Typ Max Units - 65 - °C/W ...
Page 93
... Commercial -10º to +70ºC Yes Automotive -40º to +85º Changes . . . . . Figure 18 on page 21 and . . . “Ordering Information” on page 93 CS8420 Container Order# Rail CS8420-CS Tape and Reel CS8420-CSR Rail CS8420-CSZ Tape and Reel CS8420-CSZR Rail CS8420-DSZ Tape and Reel CS8420-DSZR - - CDB8420 . . . “Serial Audio Output Port . . . 93 ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola Inc. AC registered trademark of Dolby Laboratories, Inc. I² registered trademark of Philips Semiconductor. 94 www.cirrus.com CS8420 DS245F4 ...