ADP5020 Analog Devices, ADP5020 Datasheet
ADP5020
Related parts for ADP5020
ADP5020 Summary of contents
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... The ADP5020 provides high performance, reduces component count and size, and is lower in cost when compared to conven- tional designs. The ADP5020 runs on input voltage from 2 5.5 V and supports one-cell lithium-ion (Li+) batteries. The high perfor- mance LDO maximizes noise suppression. The ADP5020 can be ...
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... ADP5020 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Applications Circuit ............................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 Switching Specifications .............................................................. 5 DC-to-DC Conversion Specifications, Buck 1 Regulator ....... 5 DC-to-DC Conversion Specifications, Buck 2 Regulator ....... 6 VOUT3 Specifications, Low Dropout (LDO) Regulator ........ Timing Specifications ............................................................ 7 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution ...
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... XSHTDN SCL SDA VDD_IO EN/GPIO SYNC THERMAL SHUTDOWN HOUSE- VDDA KEEPING VDD3 VDD2 VDD1 VDDA UVLO CONTROL LOGIC SEQUENCER DGND AGND Figure 2. Rev Page ADP5020 SW1 BUCK 1 VOUT1 VOUT1 PGND1 SW2 BUCK 2 VOUT2 PGND2 LDO VOUT3 BUCK1_EN BUCK2_EN LDO_EN ...
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... ADP5020 SPECIFICATIONS T = −40°C to +125° 3 DDx DD_IO Table 1. Parameter OPERATING RANGE VDDx Operating Voltage Range 1 Logic I/O Operating Voltage Range EN, SDA, SCL CHARACTERISTICS Low Level Input Voltage High Level Input Voltage INPUT LOGIC CURRENT XSHTDN, EN/GPIO Low Level Output Voltage ...
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... V 0.7 × V DD_IO 0 V DD_IO 0.5 1.0 V DD_IO 10 50 Min Typ Max 2.5 3.7 − LOAD −5 +4 0.2 0.15 600 4 6 175 250 250 400 0.8 1.2 1 1.4 0.7 1 1.3 ADP5020 Unit MHz MHz MHz MHz % V DD_IO μA Unit mΩ mΩ kΩ ...
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... ADP5020 DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR Table 4. Parameter OUTPUT VOLTAGE 1 Adjustable Range Initial Accuracy Total Accuracy Load Regulation Line Regulation CURRENT Maximum Output Current Quiescent Current POWER Low-Side Power nMOSFET High-Side Power pMOSFET SWITCH CURRENT LIMIT MINIMUM ON TIME MAXIMUM DUTY CYCLE SOFT START TIME ...
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... Capacitive load for each bus line of the SCL signal) to bridge the undefined region of the SCL falling edge. IHMIN t FALL FALL RISE SU,DAT t t HIGH SU,STA Sr 2 Figure Interface Timing Diagram Rev Page BUF RISE HD,STA t SU,STO P S ADP5020 ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The ADP5020 can be damaged when the junction temperature (T ) limits are exceeded. Monitoring the ambient temperature J does not guarantee that T ...
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... Exposed pad should be connected to PGND1 and PGND2. 1 PGND2 2 VOUT2 PGND2 3 VDDA VOUT2 4 AGND VDDA 5 SYNC AGND SYNC Rev Page ADP5020 PIN 1 INDICATOR 1 15 VOUT1 2 14 VOUT1 ADP5020 13 3 VDD3 TOP VIEW 4 12 VOUT3 (Not to Scale EN/GPIO Figure 5. Pin Configuration (Top View command can program ...
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... ADP5020 TYPICAL PERFORMANCE CHARACTERISTICS OUT1 OUT2 OUT3 3.5 3.3V 3.0V 3.0 2.8V 2.5V 2.5 2.0V 2.0 1.8V 1.5 1 LOAD CURRENT (mA) Figure 6. LDO Load Regulation LDO OUTPUT = 20mV/DIV I = 100mA/DIV LOAD TIME = 100µs/DIV LDO I LOAD Figure 7. LDO Load Transient 3.8 V (3.7V) 3.6 OUT7 3.4 V (3.3V) OUT6 3.2 V (3.0V) OUT4 3.0 2.8 V (2.8V) OUT2 2.6 V (2.5V) 2.4 OUT1 2 100 200 ...
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... BUCK 1 OUTPUT = 2V/DIV BUCK 2 OUTPUT = 1V/DIV TIME = 5ms/DIV BUCK 2 ENABLE BUCK 2 OUTPUT = 1V/DIV SW2 OUTPUT = 2V/DIV TIME = 500µs/DIV BUCK 2 SW2 Figure 16. Buck 2 Enable Startup BUCK 1 OUTPUT = 1V/DIV SW1 OUTPUT = 2V/DIV TIME = 500µs/DIV BUCK 1 SW1 Figure 17. Buck 1 Enable Startup ADP5020 ...
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... ADP5020 OUT1 OUT2 OUT3 LDO OUTPUT = 1V/DIV TIME = 50µs/DIV LDO Figure 18. LDO Startup SW1 BUCK 1 OUTPUT = 20mV/DIV SW1 = 5V/DIV TIME = 100ns/DIV BUCK 1 Figure 19. Buck 1 Switching Node Voltage and Output Ripple Voltage = 1 100 mA μF, C OUT ...
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... CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION Both buck converters and the LDO have a current limit feature that allows the ADP5020 to protect itself and any external compo- nents during overload and short-circuit conditions. The upper switch pMOSFET turns off if peak current exceeds the limit. ...
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... ADP5020 CONTROL REGISTERS DEVICE ADDRESS Following a start condition, the bus master must send the address of the slave it is accessing. The slave address for the ADP5020 is shown in Table 10. The Bit 0 defines the operation to be per- Table 10. Slave Address Bit 7 Bit 6 Bit 5 ADR6 ...
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... Sets the voltage output level of the LDO regulator. Preloads on power-up with values stored in fuses. Note that this value can be edited by the user in an application. 0000 = 1.8 V (default). 0001 = 1.9 V. 0010 = 2.0 V. 0011 = 2.1 V. 0100 = 2.2 V. 0101 = 2.3 V. 0110 = 2.4 V. 0111 = 2.5 V. 1000 = 2.6 V. 1001 = 2.7 V. 1010 = 2.8 V. 1011 = 2.9 V. 1100 = 3.0 V. 1101 = 3.1 V. 1110 = 3.2 V. 1111 = 3.3 V. Rev Page ADP5020 ...
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... ADP5020 Table 15. REG_CONTROL_STATUS Register, Address 0x03 Bit Bit Name Access Default 7 BK1_EN R BK2_EN R LDO_EN R EN_ALL R BK1_PGOOD BK2_PGOOD LDO_PGOOD FORCE_XS R/W 0 Table 16. OPERATIONAL_CONTROL Register, Address 0x04 Bit Bit Name Access Default 7 Reserved N/A N SYNC_9P6 R SYNC_19P2 ...
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... I C commands. Each regulator inside the ADP5020 is controlled by the sequencer block. The sequencer is factory programmed with a default turn-on sequence that determines the activation order of the regulators. The default activation order is listed as follows: 1 ...
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... ADP5020 Activation Waveforms VDDx V UVLOR POR INTERNAL POR SEQUENCER 2 REGISTERS I C BUS PROGRAMMING BUCK 1 LDO BUCK 2 XSHTDN VDDx POR INTERNAL POR SEQUENCER REGISTERS BUS PROGRAMMING BUCK 1 LDO BUCK 2 XSHTDN When activated through the EN pin, the sequencer is affected ...
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... Unused regulators can also be fuse programmed to be turned off during sequencing. <50µs t REG1 t REG2 t REG3 Figure 25. Activation and Power Failure Conditions LD0_EN BK2_EN FORCE_XS = Figure 26. Individual Activation Through I C Commands Rev Page ADP5020 V UVLOF t XSHTDN BK1_EN, FORCE_XS LDO_EN BK2_EN = 0 ...
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... ADP5020 The application processor, together with the regulator power good signal, controls the XSHTDN pin, as shown in Table 18. After a regulator is enabled and no failure condition is detected (power good = 1 in Bits[3:1] of the REG_CONTROL_STATUS register, Address 0x03), the level of the XSHTDN pin is con- trolled by Bit 0 (FORCE_XS) in the REG_CONTROL_STATUS register ...
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... Besides having the masking bits predefined through factory-programmed fuses (necessary only for operation with the EN signal), the ADP5020 provides three masking bits that are accessible through the I interface. These bits are located in the OPERATIONAL_ ...
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... L3 C8 where L3 = 250 nH, assuming that MHz and C8 = 100 nF. LC The inductor must be able to withstand the LDO load current, including the overload condition, which is limited to 400 mA. ADP5020 VBATT C1 10µF BUCK 1 (3) LDO Figure 28. Optional LDO Input Filter Rev Page ...
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... PGND1 VDD3 C6 1.0µF VDDA SW2 VOUT2 VDD_IO C5 PGND2 0.1µF VOUT3 SDA SCL SYNC EN/GPIO XSHTDN DGND AGND Figure 29. Schematic for Camera Module Applications Rev Page ADP5020 L1 2.2µH +VIS C1 10µF –VIS L2 2.2µH +V CORE C2 4.7µF –V CORE +VIO C3 1.0µF –VIO XSHTDN ...
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... ADP5020 PCB BOARD LAYOUT RECOMMENDATIONS • Place the input and output capacitors, C1, C2, C3, C4, and C5, as close as possible to the respective ADP5020 pin, and make the grounding connection to the ADP5020 ground pins as short as possible. • Connect C3, C5, and C6 to the analog ground, and connect C1, C2, and C4 to the power ground. • ...
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... Dimensions shown in millimeters Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Rev Page 2.65 EXPOSED 2.50 SQ PAD 2. 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-20-4 ADP5020 ...
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... ADP5020 NOTES Rev Page ...
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... NOTES Rev Page ADP5020 ...
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... ADP5020 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07774-0-5/09(0) Rev Page ...