ADP5020 Analog Devices, ADP5020 Datasheet - Page 14

• Manufacturer Part Number: ADP5020
• Description: Power Management Unit for Imaging Modules
• Manufacturer: Analog Devices

ADP5020
CONTROL REGISTERS
DEVICE ADDRESS
Following a start condition, the bus master must send the address
of the slave it is accessing. The slave address for the ADP5020 is
shown in Table 10. The Bit 0 defines the operation to be per-
Table 10. Slave Address
Bit 7
ADR6
0
REGISTER MAP
Table 11.
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06 to
0x0F
REGISTER DESCRIPTIONS
User Accessible Registers
Table 12. Revision Register, Address 0x00
Bit
[7:5]
[4:2]
[1:0]
Table 13. BUCK1_VSEL Register, Address 0x01
Bit
[7:3]
[2:0]
Bit Name
MAJ[2:0]
MIN[2:0]
OPT[1:0]
Bit Name
Reserved
BK1_VSEL[2:0]
Register Name
Revision
REG_CONTROL_STATUS
OPERATIONAL_CONTROL
EN_CONTROL
Reserved
BUCK1_VSEL
BUCK2_LDO_VSEL
Bit 6
ADR5
0
R
R
R/W
Access
R
Access
N/A
Bit 5
ADR4
1
Default
N/A
N/A
N/A
Default
N/A
Fuse
D7
BK1_EN
Reserved
Description
Major revision bits. Used to electronically ID the device version.
Minor revision bits. Used to electronically ID the device version.
Option bits. Used to electronically ID the option (multiple options on same device family).
Description
Reserved.
Sets the voltage output level of the Buck 1 regulator. Preloads on power-up with values
stored in fuses. Note that this value can be edited by the user in an application.
000 = 2.5 V.
001 = 2.8 V.
010 = 2.9 V.
011 = 3.0 V.
100 = 3.2 V.
101 = 3.3 V (default).
110 = 3.7 V.
111 = reserved.
D6
BK2_EN
SYNC_9P6
Bit 4
ADR3
0
MAJ[2:0]
BK2_VSEL[3:0]
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Reserved[7:3]
D5
LDO_EN
SYNC_19P2
Reserved[7:2]
Bit 3
1
ADR2
formed. When this bit is set to Logic 1, a read operation is
selected. When this bit is set to Logic 0, a write operation is
selected.
D4
EN_ALL
SYNC_
AC
D3
BK1_
PGOOD
BK1_
XSHTDN
MIN[2:0]
Bit 2
ADR1
0
D2
BK2_
PGOOD
BK2_
XSHTDN
LDO_VSEL[3:0]
D1
LDO_
PGOOD
LDO_
XSHTDN
ENO_HIZ_
BAR
Bit 1
ADR0
0
BK1_VSEL[2:0]
OPT[1:0]
Bit 0
R/W
1 or 0
D0
FORCE_XS
TSD
ENO_DRV