ADP5022 Analog Devices, ADP5022 Datasheet
ADP5022
Related parts for ADP5022
ADP5022 Summary of contents
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... The two bucks operate out-of-phase to reduce the input capacitor requirement and noise. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5022 LDO extends the battery life of portable devices. The LDO maintains power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage ...
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... ADP5022 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Buck1 and Buck2 Specifications................................................. 4 LDO Specifications ...................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Data ................................................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 10/10—Rev Rev. C Changes to Figure 2.......................................................................... 1 Changes to Table 9.......................................................................... 20 6/10— ...
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... UVLO VIN3RISE UVLO VIN3FALL UVLO High UVLO level (factory programmed) VDDARISE Low UVLO level (factory programmed) UVLO High UVLO level (factory programmed) VDDAFALL Low UVLO level (factory programmed) Rev Page ADP5022 = −40°C to +125°C, unless J Min Typ Max Unit 2.4 5.5 V 4.5 5 ...
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... ADP5022 BUCK1 AND BUCK2 SPECIFICATIONS VDDA = VIN1 = VIN2 = 3.6 V, VIN3 = (VOUT3 + 0 2.4 V, whichever is greater, VIN3 ≤ VIN1 otherwise noted. Table 2. Parameter OPERATING SUPPLY CURRENT Buck1 Only Buck2 Only Buck1 and Buck2 Only OUTPUT VOLTAGE ACCURACY POWER SAVE MODE TO PWM CURRENT THRESHOLD ...
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... Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.2 V PSRR 10 kHz, VIN3 = 5 V, VOUT3 = 3 kHz, VIN3 = 5 V, VOUT3 = 2 kHz, VIN3 = 5 V, VOUT3 = 1 and I specifications. GND1 GND2 GND1-2 Rev Page ADP5022 = 10 mA OUT3 IN3 OUT3 Min Typ Max ...
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... THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP5022 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature (T not guarantee that the junction temperature (T specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated ...
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... Buck2 Output Voltage Sensing Input. D4 PGND2 Dedicated Power Ground for Buck2. BALL A1 INDICATOR VOUT3 AGND VIN3 VDDA A VIN1 EN1 EN2 VIN2 B SW1 EN3 MODE SW2 C PGND1 VOUT1 VOUT2 PGND2 D TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 3. Pin Configuration Rev Page ADP5022 ...
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... ADP5022 TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3 = VDDA = 5 VOUT1 1 VOUT2 2 VOUT3 3 CH1 2.00V CH2 2.00V M 200µ CH3 2.00V 45.40% Figure 4. 3-Channel Start-Up Waveforms, VIN3 Cascaded from VOUT1 0.00010 0.00008 0.00006 0.00004 0.00002 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 V (V) IN Figure 5. System Quiescent Current vs. Input Voltage, VOUT1 = 0.8 V, VOUT2 = 2 ...
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... Figure 14. Buck1 Efficiency vs. Load Current, Across Input Voltage, 100 0.5 0.6 0.0001 Figure 15. Buck2 Efficiency vs. Load Current, Across Input Voltage, Rev Page ADP5022 5.5V IN 0.001 0.01 0 (A) OUT VOUT1 = 3.3 V, Auto Mode ...
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... ADP5022 100 0.001 0.01 I (A) OUT Figure 16. Buck2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, PWM Mode 100 0.0001 0.001 0.01 I (A) OUT Figure 17. Buck1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, Auto Mode ...
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... PWM Mode OUT2 T VIN VOUT SW CH1 50.0mV M 1.00ms A CH3 B W CH3 1.00V CH4 2.00V 30.40% 5.0 V, VOUT1 = 3.3 V, PWM Mode T VIN VOUT SW M 1.00ms A CH3 B W 1.00V CH4 2.00V 30.40 VOUT2 = 1.8 V, PWM Mode ADP5022 220mA 4.80V 4.80V ...
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... ADP5022 VOUT 1 I OUT 2 CH1 50.0mV CH2 50.0mA Ω M 20.0µs A CH2 CH4 5.00V T 60.000µ Figure 28. Buck1 Response to Load Transient, I VOUT1 = 3.3 V, Auto Mode VOUT 1 I OUT 2 CH1 50.0mV CH2 50.0mA Ω M 20.0µs A CH2 CH4 5.00V ...
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... Figure 39. LDO Current Capability Across Input Voltage, VOUT3 = 2.8 V Rev Page 3.3 3.8 4.3 4.8 INPUT VOLTAGE (V) VOUT3 = 2 0.02 0.04 0.06 0.08 0.10 LOAD CURRENT (A) 3.0 2.5 2.0 1 4. 0.05 0.10 0.15 0.20 0.25 0.30 I (A) OUT ADP5022 150mA 100mA 10mA 1mA 100µA 1µA 5.3 0.12 0.14 0.35 0.40 ...
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... ADP5022 T I OUT 2 VOUT 1 CH1 100mV CH2 100mA Ω M 40.0µs A CH2 19.20% Figure 40. LDO Response to Load Transient, I VOUT3 = 2 VIN VOUT CH1 20.0mV M 100µ CH3 1.00V 28.40% Figure 41. LDO Response to Line Transient, Input Voltage from 4 5.5 V, VOUT3 = 2.8 V ...
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... Figure 46. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 1M 10M 10 Figure 47. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V Rev Page ADP5022 100µA 1mA 10mA 50mA 100mA 150mA 100 1k 10k 100k 1M FREQUENCY (Hz) 10M ...
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... CONTROL EN3 VDDA VIN3 POWER MANAGEMENT UNIT The ADP5022 is a micro power management units (micro PMU) combining two step-down (buck) dc-to-dc converters and a single low dropout linear regulator (LDO). The high switching frequency and tiny 16-ball WLCSP package allow for a small power management solution. ...
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... The PSM current threshold is optimized for excellent efficiency over all load currents. Oscillator/Phasing of Inductor Switching The ADP5022 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. Additionally, the ADP5022 ensures that when both bucks are ...
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... The ADP5022 integrates an undervoltage lockout function on the VIN3 input voltage, which ensures that the LDO output drive is disabled whenever VIN3 is below a threshold of approximately 2.0 V. Where the ADP5022 is configured to supply VIN3 from either VOUT1 or VOUT2, this ensures that the LDO powers up safely in this cascaded configuration. ...
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... Figure 1. Inductor The high switching frequency of the ADP5022 bucks allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 μH and 3 μH. Suggested inductors are shown in Table 7. ...
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... A minimum of 0.70 μF capacitance with an ESR of 1 Ω or less is recommended to ensure stability of the ADP5022. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacit- L1 ance improves the transient response of the ADP5022 to large PROCESSOR 1µH changes in load current. VCORE ...
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... Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5022 imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. ...
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... ADP5022 PCB LAYOUT GUIDELINES Poor layout can affect ADP5022 performance, causing electro- magnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: • ...
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... EN3 Figure 52. Evaluation Board Schematic Figure 53. Top Layer, Recommended Layout Figure 54. Second Layer, Recommended Layout Rev Page 1µ OUT D2 0603 J9 10µ 1µH J10 OUT D3 0603 J13 10µF D4 J12 OUT 0402 J11 1µF ADP5022 ...
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... ADP5022 Figure 55. Third Layer, Recommended Layout Figure 56. Bottom Layer, Recommended Layout Rev Page ...
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... Wafer Level Chip Scale Package [WLCSP] −40°C to +125°C 16-Ball Wafer Level Chip Scale Package [WLCSP] −40°C to +125°C 16-Ball Wafer Level Chip Scale Package [WLCSP] Additional output voltages and UVLO available are Rev Page ADP5022 ...
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... ADP5022 NOTES Rev Page ...
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... NOTES Rev Page ADP5022 ...
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... ADP5022 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08253-0-10/10(C) Rev Page ...