ADP5022

Manufacturer Part NumberADP5022
DescriptionDual 3 MHz, 600 mA Buck Regulator with 150 mA LDO
ManufacturerAnalog Devices
ADP5022 datasheet
 


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FEATURES
Input voltage range: 2.4 V to 5.5 V
Tiny 16-ball, 2 mm × 2 mm WLCSP package
Overcurrent and thermal protection
Soft start
Factory programmable undervoltage lockout on VDDA
system supply of either 2.2 V or 3.9 V
Factory programmable default output voltages for all
3 channels
Buck1 and Buck2 key specifications
Current mode architecture for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Forced PWM and auto PWM/PSM modes
Out-of-phase operation for reduced input filtering
100% duty cycle low dropout mode
24 μA typical quiescent current per channel, no switching
LDO key specifications
Stable with 1 μF ceramic output capacitors
High PSRR
60 dB up to 10 KHz
Low output noise
65 μV rms output noise at VOUT3 = 3.3 V
Low dropout voltage: 150 mV @ 150 mA load
11 μA typical ground current at no load
APPLICATIONS
USB devices
Handheld products
Multivoltage power for processors, ASICS, FPGAs,
and RF chipsets
ADP5022
V
= 2.4V
VIN1
IN
TO 5.5V
ON
C2
EN1
4.7µF
OFF
VIN2
C3
4.7µF
ON
EN2
OFF
VDDA
C1
VIN3
1µF
ON
EN3
OFF
Figure 1. Typical Applications Circuit
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
GENERAL DESCRIPTION
The ADP5022 is a micro power management unit (micro PMU)
that combines two high performance buck regulators and a low
dropout regulator (LDO) in a tiny 16-ball 2.08 mm × 2.08 mm
WLCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulators enables
tiny multilayer external components and minimizes the board
space required. When the MODE pin is set high, the buck reg-
ulators operate in forced PWM mode. When the MODE pin is
set low, the buck regulators automatically switch operating
modes, depending on the load current level. At higher output
loads, the buck regulators operate in PWM mode. When the
load current falls below a predefined threshold, the regulators
operate in power save mode (PSM), improving the light-load
efficiency.
The two bucks operate out-of-phase to reduce the input
capacitor requirement and noise.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5022 LDO extends the battery life of
portable devices. The LDO maintains power supply rejection
greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.
Each regulator in the ADP5022 has a dedicated, independent
enable pin. A high voltage level applied to the enable pin activates
the respective regulator. The default output voltages are factory
programmable and can be set to a wide range of options.
L1
1µH
SW1
BUCK1
VOUT1
C4
10µF
PGND1
EN_BK1
MODE
PWM
MODE
PWM/PSM
L2
1µH
MODE
SW2
BUCK2
VOUT2
C5
10µF
PGND2
EN_BK2
VOUT3
LDO1
C6
EN_LDO1
1µF
AGND
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Dual 3 MHz, 600 mA Buck
Regulator with 150 mA LDO
ADP5022
COUT_3
V
@
OUT1
600mA
C3
C1
V
@
OUT2
600mA
V
@
OUT3
150mA
L1
COUT_1
COUT_2
4.7mm
Figure 2. Typical PCB Layout
©2009–2010 Analog Devices, Inc. All rights reserved.
C4
C2
5.0mm
www.analog.com

ADP5022 Summary of contents

  • Page 1

    ... The two bucks operate out-of-phase to reduce the input capacitor requirement and noise. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5022 LDO extends the battery life of portable devices. The LDO maintains power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage ...

  • Page 2

    ... ADP5022 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Buck1 and Buck2 Specifications................................................. 4 LDO Specifications ...................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Data ................................................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 10/10—Rev Rev. C Changes to Figure 2.......................................................................... 1 Changes to Table 9.......................................................................... 20 6/10— ...

  • Page 3

    ... UVLO VIN3RISE UVLO VIN3FALL UVLO High UVLO level (factory programmed) VDDARISE Low UVLO level (factory programmed) UVLO High UVLO level (factory programmed) VDDAFALL Low UVLO level (factory programmed) Rev Page ADP5022 = −40°C to +125°C, unless J Min Typ Max Unit 2.4 5.5 V 4.5 5 ...

  • Page 4

    ... ADP5022 BUCK1 AND BUCK2 SPECIFICATIONS VDDA = VIN1 = VIN2 = 3.6 V, VIN3 = (VOUT3 + 0 2.4 V, whichever is greater, VIN3 ≤ VIN1 otherwise noted. Table 2. Parameter OPERATING SUPPLY CURRENT Buck1 Only Buck2 Only Buck1 and Buck2 Only OUTPUT VOLTAGE ACCURACY POWER SAVE MODE TO PWM CURRENT THRESHOLD ...

  • Page 5

    ... Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.2 V PSRR 10 kHz, VIN3 = 5 V, VOUT3 = 3 kHz, VIN3 = 5 V, VOUT3 = 2 kHz, VIN3 = 5 V, VOUT3 = 1 and I specifications. GND1 GND2 GND1-2 Rev Page ADP5022 = 10 mA OUT3 IN3 OUT3 Min Typ Max ...

  • Page 6

    ... THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP5022 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature (T not guarantee that the junction temperature (T specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated ...

  • Page 7

    ... Buck2 Output Voltage Sensing Input. D4 PGND2 Dedicated Power Ground for Buck2. BALL A1 INDICATOR VOUT3 AGND VIN3 VDDA A VIN1 EN1 EN2 VIN2 B SW1 EN3 MODE SW2 C PGND1 VOUT1 VOUT2 PGND2 D TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 3. Pin Configuration Rev Page ADP5022 ...

  • Page 8

    ... ADP5022 TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3 = VDDA = 5 VOUT1 1 VOUT2 2 VOUT3 3 CH1 2.00V CH2 2.00V M 200µ CH3 2.00V 45.40% Figure 4. 3-Channel Start-Up Waveforms, VIN3 Cascaded from VOUT1 0.00010 0.00008 0.00006 0.00004 0.00002 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 V (V) IN Figure 5. System Quiescent Current vs. Input Voltage, VOUT1 = 0.8 V, VOUT2 = 2 ...

  • Page 9

    ... Figure 14. Buck1 Efficiency vs. Load Current, Across Input Voltage, 100 0.5 0.6 0.0001 Figure 15. Buck2 Efficiency vs. Load Current, Across Input Voltage, Rev Page ADP5022 5.5V IN 0.001 0.01 0 (A) OUT VOUT1 = 3.3 V, Auto Mode ...

  • Page 10

    ... ADP5022 100 0.001 0.01 I (A) OUT Figure 16. Buck2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, PWM Mode 100 0.0001 0.001 0.01 I (A) OUT Figure 17. Buck1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, Auto Mode ...

  • Page 11

    ... PWM Mode OUT2 T VIN VOUT SW CH1 50.0mV M 1.00ms A CH3 B W CH3 1.00V CH4 2.00V 30.40% 5.0 V, VOUT1 = 3.3 V, PWM Mode T VIN VOUT SW M 1.00ms A CH3 B W 1.00V CH4 2.00V 30.40 VOUT2 = 1.8 V, PWM Mode ADP5022 220mA 4.80V 4.80V ...

  • Page 12

    ... ADP5022 VOUT 1 I OUT 2 CH1 50.0mV CH2 50.0mA Ω M 20.0µs A CH2 CH4 5.00V T 60.000µ Figure 28. Buck1 Response to Load Transient, I VOUT1 = 3.3 V, Auto Mode VOUT 1 I OUT 2 CH1 50.0mV CH2 50.0mA Ω M 20.0µs A CH2 CH4 5.00V ...

  • Page 13

    ... Figure 39. LDO Current Capability Across Input Voltage, VOUT3 = 2.8 V Rev Page 3.3 3.8 4.3 4.8 INPUT VOLTAGE (V) VOUT3 = 2 0.02 0.04 0.06 0.08 0.10 LOAD CURRENT (A) 3.0 2.5 2.0 1 4. 0.05 0.10 0.15 0.20 0.25 0.30 I (A) OUT ADP5022 150mA 100mA 10mA 1mA 100µA 1µA 5.3 0.12 0.14 0.35 0.40 ...

  • Page 14

    ... ADP5022 T I OUT 2 VOUT 1 CH1 100mV CH2 100mA Ω M 40.0µs A CH2 19.20% Figure 40. LDO Response to Load Transient, I VOUT3 = 2 VIN VOUT CH1 20.0mV M 100µ CH3 1.00V 28.40% Figure 41. LDO Response to Line Transient, Input Voltage from 4 5.5 V, VOUT3 = 2.8 V ...

  • Page 15

    ... Figure 46. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 1M 10M 10 Figure 47. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V Rev Page ADP5022 100µA 1mA 10mA 50mA 100mA 150mA 100 1k 10k 100k 1M FREQUENCY (Hz) 10M ...

  • Page 16

    ... CONTROL EN3 VDDA VIN3 POWER MANAGEMENT UNIT The ADP5022 is a micro power management units (micro PMU) combining two step-down (buck) dc-to-dc converters and a single low dropout linear regulator (LDO). The high switching frequency and tiny 16-ball WLCSP package allow for a small power management solution. ...

  • Page 17

    ... The PSM current threshold is optimized for excellent efficiency over all load currents. Oscillator/Phasing of Inductor Switching The ADP5022 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. Additionally, the ADP5022 ensures that when both bucks are ...

  • Page 18

    ... The ADP5022 integrates an undervoltage lockout function on the VIN3 input voltage, which ensures that the LDO output drive is disabled whenever VIN3 is below a threshold of approximately 2.0 V. Where the ADP5022 is configured to supply VIN3 from either VOUT1 or VOUT2, this ensures that the LDO powers up safely in this cascaded configuration. ...

  • Page 19

    ... Figure 1. Inductor The high switching frequency of the ADP5022 bucks allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 μH and 3 μH. Suggested inductors are shown in Table 7. ...

  • Page 20

    ... A minimum of 0.70 μF capacitance with an ESR of 1 Ω or less is recommended to ensure stability of the ADP5022. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacit- L1 ance improves the transient response of the ADP5022 to large PROCESSOR 1µH changes in load current. VCORE ...

  • Page 21

    ... Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5022 imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. ...

  • Page 22

    ... ADP5022 PCB LAYOUT GUIDELINES Poor layout can affect ADP5022 performance, causing electro- magnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: • ...

  • Page 23

    ... EN3 Figure 52. Evaluation Board Schematic Figure 53. Top Layer, Recommended Layout Figure 54. Second Layer, Recommended Layout Rev Page 1µ OUT D2 0603 J9 10µ 1µH J10 OUT D3 0603 J13 10µF D4 J12 OUT 0402 J11 1µF ADP5022 ...

  • Page 24

    ... ADP5022 Figure 55. Third Layer, Recommended Layout Figure 56. Bottom Layer, Recommended Layout Rev Page ...

  • Page 25

    ... Wafer Level Chip Scale Package [WLCSP] −40°C to +125°C 16-Ball Wafer Level Chip Scale Package [WLCSP] −40°C to +125°C 16-Ball Wafer Level Chip Scale Package [WLCSP] Additional output voltages and UVLO available are Rev Page ADP5022 ...

  • Page 26

    ... ADP5022 NOTES Rev Page ...

  • Page 27

    ... NOTES Rev Page ADP5022 ...

  • Page 28

    ... ADP5022 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08253-0-10/10(C) Rev Page ...