ADP5022 Analog Devices, ADP5022 Datasheet - Page 6

• Manufacturer Part Number: ADP5022
• Description: Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO
• Manufacturer: Analog Devices

ADP5022
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VDDA, VIN1, VIN2, VIN3, VOUT1, VOUT2,
VOUT3, EN1, EN2, EN3, MODE to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP5022 can be damaged when the junction temperature
limits are exceeded. Monitoring ambient temperature (T
not guarantee that the junction temperature (T
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated. In applications with
moderate power dissipation and low PCB thermal resistance,
the maximum ambient temperature may exceed the maximum
limit as long as the junction temperature is within specification
limits. T
dissipation (P
thermal resistance (θ
calculated from T
T
J
= T
J
of the device is dependent on T
A
+ (P
D
) of the device, and the junction-to-ambient
D
A
× θ
and P
JA
JA
) of the package. Maximum T
)
D
using the following formula:
A
, the power
Rating
−0.3 V to +6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
J
) is within the
J
is
A
) does
Rev. C | Page 6 of 28
θ
4-layer board. The junction-to-ambient thermal resistance is
highly dependent on the application and board layout. In
applications where high maximum power dissipation exists,
close attention to thermal board design is required. The value
of θ
ronmental conditions. The specified values of θ
4-layer, 4” × 3” circuit board. Refer to JEDEC JESD 51-9 for
detailed information on the board construction. For additional
information, see the AN-617 Application Note, MicroCSP
Wafer Level Chip Scale Package.
THERMAL RESISTANCE
θ
soldered on a circuit board.
Table 5. Thermal Resistance
Package Type
16-Ball, 0.5 mm Pitch WLCSP
ESD CAUTION
JA
JA
of the package is based on modeling and calculation using a
is specified for the worst-case conditions, that is, a device
JA
may vary, depending on PCB material, layout, and envi-
θ
65
JA
JA
are based on a
Unit
°C/W
TM