ADP5024 Analog Devices, ADP5024 Datasheet - Page 25

• Manufacturer Part Number: ADP5024
• Description: Dual 3 MHz, 1200 mA Buck Regulators with One 300 mA LDO
• Manufacturer: Analog Devices

Data Sheet
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
where:
C
C
For the ADP5024, the total of (C
imately 150 pF.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SW node takes some time to slew from near ground to near
V
loss is calculated by
where t
switching node, SW. For the ADP5024, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for estimating
the converter efficiency, it must be noted that the equations do
not describe all of the converter losses, and the parameter values
given are typical numbers. The converter performance also
depends on the choice of passive components and board layout;
therefore, include a sufficient safety margin in the estimate.
LDO Regulator Power Dissipation
The power loss of the LDO regulator is given by
where:
I
V
respectively.
I
Power dissipation due to the ground current is small, and it
can be ignored.
The total power dissipation in the
LOAD
GND
GATE-P
GATE-N
IN
OUT1
and V
is the ground current of the LDO regulator.
P
P
P
P
is the load current of the LDO regulator.
(and from V
SW
TRAN
DLDO
D
is the P-MOSFET gate capacitance.
is the N-MOSFET gate capacitance.
RISE
= P
= (C
OUT
= V
= [(V
and t
DBUCK1
GATE-P
are input and output voltages of the LDO,
IN1
FALL
IN
× I
+ P
− V
OUT1
+ C
OUT1
are the rise time and the fall time of the
DBUCK2
OUT
GATE-N
to ground). The amount of transition
× (t
) × I
+ P
) × V
RISE
LOAD
DLDO
+ t
IN1
GATE-P
] + (V
FALL
ADP5024
2
× f
) × f
+ C
SW
IN
× I
SW
GATE-N
GND
simplifies to
) is approx-
)
(10)
(11)
(12)
(13)
Rev. A | Page 25 of 28
JUNCTION TEMPERATURE
In cases where the board temperature, T
thermal resistance parameter, θ
junction temperature rise. T
the formula
The typical θ
35°C/W (see Table 6). A very important factor to consider is
that θ
JEDEC standard, and real applications may use different sizes
and layers. To remove heat from the device, it is important to
maximize the use of copper. Copper exposed to air dissipates
heat better than copper used in the inner layers. Connect the
exposed pad to the ground plane with several vias.
If the case temperature can be measured, the junction temperature
is calculated by
where T
thermal resistance provided in Table 6.
When designing an application for a particular ambient
temperature range, calculate the expected
dissipation (P
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
The reliable operation of the converter and the LDO regulator
can be achieved only if the estimated die junction temperature of
the
and mean time between failures (MTBF) is highly affected by
increasing the junction temperature. Additional information
about product reliability can be found from the ADI Reliability
Handbook, which is available at the following URL:
www.analog.com/reliability_handbook.
ADP5024
T
T
JA
J
J
= T
= T
is based on a 4-layer, 4 in × 3 in, 2.5 oz copper, as per
C
is the case temperature and θ
A
C
+ (P
+ (P
JA
D
(see Equation 14) is less than 125°C. Reliability
) due to the losses of all channels by using
value for the 24-lead, 4 mm × 4 mm LFCSP is
D
D
× θ
× θ
JC
JA
)
)
J
, can be estimated using Equation 14.
J
is calculated from T
JA
, can be used to estimate the
JC
A
is the junction-to-case
, is known, the
ADP5024
A
ADP5024
and P
power
D
using
(14)
(15)