ADP5033

Manufacturer Part NumberADP5033
DescriptionDual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs
ManufacturerAnalog Devices
ADP5033 datasheet
 


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Data Sheet
FEATURES
Main input voltage range: 2.3 V to 5.5 V
Two 800 mA buck regulators and two 300 mA LDOs
Tiny, 16-ball, 2 mm × 2 mm WLCSP package
Regulator accuracy: ±3%
Factory programmable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.3 V
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V
LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V
LDO1/LDO2: high PSRR and low output noise
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
The
ADP5033
combines two high performance buck regulators
and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm ×
2 mm WLCSP to meet demanding performance and board
space requirements.
2.3V TO 5.5V
1.7V TO 5.5V
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Regulators with Two 300 mA LDOs
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set high, the buck regulators operate in
forced PWM mode. When the MODE pin is set low, the buck
regulators operate in PWM mode when the load current is above
a predefined threshold. When the load current falls below a
predefined threshold, the regulator operates in power save
mode (PSM), improving the light load efficiency.
The two bucks operate out of phase to reduce the input capacitor
requirement and noise.
The low quiescent current, low dropout voltage, and wide input
voltage range of the
portable devices. The
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
The regulators in the
pins. The specific channels controlled by ENA and ENB are set
by factory programming. A high voltage level applied to the enable
pins activates the regulators. The default output voltages are
factory programmable and can be set to a wide range of options.
TYPICAL APPLICATION CIRCUIT
ADP5033
SW1
VIN1
VOUT1
C1
BUCK1
4.7µF
PGND1
EN1
ENA
MODE
ON
EN2
OFF
ENB
EN3
MODE
EN4
VIN2
MODE
C2
SW2
4.7µF
VOUT2
BUCK2
PGND2
EN2
EN3
VOUT3
VIN3
LDO1
C3
(ANALOG)
1µF
EN4
VOUT4
VIN4
LDO2
C4
(DIGITAL)
1µF
AGND
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Dual 3 MHz, 800 mA Buck
ADP5033
ADP5033
LDO extend the battery life of
ADP5033
LDOs maintain power supply
ADP5033
are activated by the ENA and ENB
L1 1µH
VOUT1 @
800mA
C5
10µF
PWM
PSM/PWM
L2 1µH
VOUT2 @
800mA
C6
10µF
VOUT3 @
300mA
C7
1µF
VOUT4 @
300mA
C8
1µF
www.analog.com
©2011–2012 Analog Devices, Inc. All rights reserved.

ADP5033 Summary of contents

  • Page 1

    ... Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Dual 3 MHz, 800 mA Buck ADP5033 ADP5033 LDO extend the battery life of ADP5033 LDOs maintain power supply ADP5033 are activated by the ENA and ENB L1 1µH VOUT1 @ 800mA C5 10µF ...

  • Page 2

    ... ADP5033 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 General Specifications ................................................................. 3 BUCK1 and BUCK2 Specifications ........................................... 4 LDO1 and LDO2 Specifications................................................. 4 Input and Output Capacitor, Recommended Specifications.. 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ...

  • Page 3

    ... STBY-NOSW −40°C to +85°C SHUTDOWN J UVLO VIN1RISE UVLO VIN1FALL UVLO VIN1RISE UVLO VIN1FALL to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal levels. VIN1RISE Rev Page ADP5033 Min Typ Max Unit 2.3 5.5 V 150 °C 20 °C 250 μs 300 μs 1 ...

  • Page 4

    ... ADP5033 BUCK1 AND BUCK2 SPECIFICATIONS 2 5 −40°C to +125°C for minimum/maximum specifications, and T IN1 IN2 J 1 otherwise noted. Table 2. Parameter Symbol INPUT CHARACTERISTICS Input Voltage Range IN1 IN2 OUTPUT CHARACTERISTICS Output Voltage Accuracy ∆V /V OUT1 Line Regulation (∆ ...

  • Page 5

    ... OUT3 = 2 OUT3 = OUT3 = 1 OUT4 = 1 OUT4 = OUT4 Min Typ Max 4.7 40 MIN2 10 40 MIN2 1.0 MIN4 0.001 1 ADP5033 Max Unit mV 110 Ω Unit μF μF μF Ω ...

  • Page 6

    ... ADP5033 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter VIN1 to AGND VIN2 to VIN1 PGND1, PGND2 to AGND VIN3, VIN4, VOUT1, VOUT2, ENA, ENB, MODE to AGND VOUT3 to AGND VOUT4 to AGND SW1 to PGND1 SW2 to PGND2 Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...

  • Page 7

    ... Dedicated Power Ground for BUCK2. BALL A1 INDICATOR VOUT3 VIN3 VIN4 VOUT4 A AGND MODE ENA ENB B VIN1 VOUT1 VOUT2 VIN2 C PGND1 SW1 SW2 PGND2 D TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 2. Pin Configuration—View from the Top of the Die Rev Page ADP5033 ...

  • Page 8

    ... ADP5033 TYPICAL PERFORMANCE CHARACTERISTICS 3 25°C, unless otherwise noted. IN1 IN2 IN3 IN4 A 140 120 100 2.3 2.8 3.3 3.8 INPUT VOLTAGE (V) Figure 3. System Quiescent Current vs. Input Voltage 1 1 3.3 V, All Channels Unloaded OUT2 OUT3 OUT4 IOUT 2 VOUT CH1 2 ...

  • Page 9

    ... OUT2 100 0.001 0.01 0.1 I (A) OUT V = 0.8 V, Auto Mode OUT1 100 0.001 0.01 0.1 I (A) OUT V = 0.8 V, PWM Mode OUT1 ADP5033 ...

  • Page 10

    ... ADP5033 100 0.001 0.01 I (A) OUT Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature 3 3.3 V, Auto Mode IN1 OUT1 100 0.001 0.01 I (A) OUT Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature 1.8 V, Auto Mode ...

  • Page 11

    ... M 20.0µs A CH2 CH4 5.00V T 60.000µs OUT1 V = 3.3 V, Auto Mode OUT1 VOUT 1 I OUT 2 CH1 50.0mV CH2 50.0mA Ω M 20.0µs A CH2 CH4 5.00V T 22.20% OUT2 V = 1.8 V, Auto Mode OUT2 ADP5033 4.80V = 4 5.0 V, 356mA from mA, 379mA from mA, ...

  • Page 12

    ... ADP5033 VOUT 1 I OUT 2 CH1 50.0mV CH2 200mA Ω M 20.0µs A CH2 CH4 5.00V T 20.40% Figure 27. BUCK1 Response to Load Transient 3.3 V, Auto Mode OUT1 VOUT 1 I OUT 2 CH1 100mV CH2 200mA Ω M 20.0µs A CH2 CH4 5.00V T 19.20% Figure 28. BUCK2 Response to Load Transient ...

  • Page 13

    ... VIN VOUT CH1 20.0mV M 100µs A CH3 CH3 1.00V T 28.40 2.8 V OUT3 3. 0.001 0.01 0 (mA) LOAD V = 2.8 V OUT3 3. 0.001 0.01 0 (mA) LOAD V = 3.0 V OUT3 ADP5033 4.80V 100 100 ...

  • Page 14

    ... ADP5033 0 100µA –10 1mA 10mA –20 50mA 100mA –30 150mA –40 –50 –60 –70 –80 –90 –100 10 100 1k 10k FREQUENCY (Hz) Figure 39. LDO PSRR Across Output Load –20 –40 –60 –80 –100 –120 10 100 1k 10k FREQUENCY (Hz) Figure 40. LDO PSRR Across Output Load, V ...

  • Page 15

    ... the duty cycle. (2b) The ADP5033 the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator ...

  • Page 16

    ... RISE FALL switching node, SW. For the ADP5033, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimat- ing the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers ...

  • Page 17

    ... PWM COMP SOFT START I LIMIT PSM COMP PWM/ PSM CONTROL LOW BUCK2 CURRENT DRIVER AND ANTISHOOT THROUGH OPMODE SEL MODE2 B ENLDO1 600Ω LDO UNDERVOLTAGE LOCK OUT R3 LDO CONTROL VDDA ENLDO1 600Ω R4 VIN4 ADP5033 VIN2 SW2 PGND2 MODE VOUT4 ...

  • Page 18

    ... The synchronous rectifier stays on for the rest of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold. Figure 44. Regulators Sequencing on the ADP5033 Rev Page Data Sheet VUVLO VPOR 30µs (MIN) 50µs (MIN) (ENx = VINx) ADP5033 ...

  • Page 19

    ... LDO1 is optimized to supply analog circuits because it offers better noise performance compared to LDO2. LDO1 should be used in applications where noise performance is critical. Rev Page ADP5033 ...

  • Page 20

    ... Figure 1. Inductor The high switching frequency of the ADP5033 the selection of small chip inductors. For best performance, use inductor values between 0.7 μH and 3 μH. Suggested inductors are shown in Table 8. The peak-to-peak inductor current ripple is calculated using the following equation: × ...

  • Page 21

    ... PSM mode (see Figure 47). Model GRM188R60J106 C1608JB0J106K ECJ1VB0J106M Rev Page ADP5033 Case Size Voltage Rating (V) 0603 6.3 0603 6.3 0603 6.3 ...

  • Page 22

    ... LDO over 0402 6.3 temperature and tolerance at the chosen output voltage. 0402 10.0 To guarantee the performance of the ADP5033 imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. ADP5033 as Rev Page ...

  • Page 23

    ... Maximize the size of ground metal on the component side to help with thermal dissipation. • Use a ground plane with several vias connecting to the component side ground to further reduce noise interfer- ence on sensitive circuit nodes. • Connect VIN1 and VIN2 together close to the IC using short tracks. Rev Page ADP5033 ...

  • Page 24

    ... ADP5033 TYPICAL APPLICATION SCHEMATIC VIN: 2.3V TO 5.5V FROM VIO (1.7V MIN) FROM VCORE (1.7V MIN) Figure 47. Processor System Power Management with PSM/PWM Control ADP5033 L1 1µH SW1 VIN1 VOUT1 C1 BUCK1 4.7µF PGND1 ALWAYS ON ENA BK1 BK2 MODE ON ACT LD1 OFF ENB LD2 VIN2 L2 1µH ...

  • Page 25

    ... LDO1 VOUT3: 2 all VOUT4: 3.0 V channels Additional options available include the following: Rev Page 1.50 REF C D 0.50 REF BOTTOM VIEW (BALL SIDE UP) Package Package 3 Description Option 16-Ball WLCSP CB-16-7 16-Ball WLCSP CB-16-7 Evaluation Board for ADP5033ACBZ-1-R7 ADP5033 Branding LHX LMD ...

  • Page 26

    ... ADP5033 NOTES Rev Page Data Sheet ...

  • Page 27

    ... Data Sheet NOTES Rev Page ADP5033 ...

  • Page 28

    ... ADP5033 NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09788-0-1/12(A) Rev Page Data Sheet ...