ADP5033 Analog Devices, ADP5033 Datasheet - Page 16

• Manufacturer Part Number: ADP5033
• Description: Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs
• Manufacturer: Analog Devices

ADP5033
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
where:
C
C
For the ADP5033, the total of (C
mately 150 pF.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SW node takes some time to slew from near ground to near
V
loss is calculated by
where t
switching node, SW. For the ADP5033, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for estimat-
ing the converter efficiency, it must be noted that the equations
do not describe all of the converter losses, and the parameter
values given are typical numbers. The converter performance
also depends on the choice of passive components and board
layout; therefore, a sufficient safety margin should be included
in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by
where:
I
V
respectively.
I
Power dissipation due to the ground current is small, and it
can be ignored.
The total power dissipation in the
LOAD
GND
GATE-P
GATE-N
OUT1
IN
and V
is the ground current of the LDO regulator.
P
P
P
P
is the load current of the LDO regulator.
(and from V
SW
TRAN
DLDO
D
is the P-MOSFET gate capacitance.
is the N-MOSFET gate capacitance.
RISE
= P
= (C
OUT
= V
= [(V
and t
DBUCK1
GATE-P
are input and output voltages of the LDO,
IN1
FALL
IN
× I
+ P
− V
OUT1
+ C
are the rise time and the fall time of the
OUT1
DBUCK2
OUT
GATE-N
to ground). The amount of transition
× (t
) × I
+ P
) × V
RISE
LOAD
DLDO1
+ t
GATE-P
IN1
] + (V
FALL
ADP5033
2
+ P
× f
) × f
+ C
DLDO2
SW
IN
× I
SW
GATE-N
GND
simplifies to
) is approxi-
)
(10)
(11)
(12)
(13)
Rev. A | Page 16 of 28
JUNCTION TEMPERATURE
In cases where the board temperature T
resistance parameter, θ
temperature rise. T
formula
The typical θ
57°C/W (see Table 6). A very important factor to consider is
that θ
JEDEC standard, and real applications may use different sizes
and layers. It is important to maximize the copper used to remove
the heat from the device. Copper exposed to air dissipates heat
better than copper used in the inner layers. The exposed pad
should be connected to the ground plane with several vias.
If the case temperature can be measured, the junction tempera-
ture is calculated by
where T
board thermal resistance provided in Table 6.
When designing an application for a particular ambient
temperature range, calculate the expected
dissipation (P
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
The reliable operation of the converter and the two LDO regulators
can be achieved only if the estimated die junction temperature of
the
mean time between failures (MTBF) is highly affected by increas-
ing the junction temperature. Additional information about
product reliability can be found in the ADI Reliability Handbook,
which can be found at www.analog.com/reliability_handbook.
ADP5033
T
T
JA
J
J
= T
= T
is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per
C
is the case temperature and Ψ
A
C
+ (P
+ (P
JA
D
(Equation 14) is less than 125°C. Reliability and
) due to the losses of all channels by using the
value for the 16-ball, 0.5 mm pitch WLCSP is
D
D
× Ψ
× θ
J
is calculated from T
JA
JB
JA
)
)
J
, can be used to estimate the junction
, can be estimated using Equation 14.
JB
A
A
is known, the thermal
is the junction-to-
and P
ADP5033
Data Sheet
D
using the
power
(14)
(15)