ADP5033 Analog Devices, ADP5033 Datasheet - Page 23

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ADP5033

Manufacturer Part Number
ADP5033
Description
Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs
Manufacturer
Analog Devices
Datasheet

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Data Sheet
PCB LAYOUT GUIDELINES
Poor layout can affect
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
ADP5033
performance, causing electro-
Rev. A | Page 23 of 28
Maximize the size of ground metal on the component side
to help with thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise interfer-
ence on sensitive circuit nodes.
Connect VIN1 and VIN2 together close to the IC using
short tracks.
ADP5033

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