ADP5034

Manufacturer Part NumberADP5034
DescriptionDual 3 MHz, 1200mA Buck Regulator with Two 300 mA LDOs
ManufacturerAnalog Devices
ADP5034 datasheet
 


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Data Sheet
FEATURES
Main input voltage range: 2.3 V to 5.5 V
Two 1200 mA buck regulators and two 300 mA LDOs
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±3%
Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V
LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V
LDO1/LDO2: high PSRR and low output noise
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
The ADP5034 combines two high performance buck regulators
and two low dropout (LDO) regulators in a small, 24-lead 4 mm ×
2.3V TO
5.5V
1.7V TO
5.5V
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Regulators with Two 300 mA LDOs
4 mm LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set to high, the buck regulators operate in
forced PWM mode. When the MODE pin is set to low, the buck
regulators operate in PWM mode when the load is above a pre-
defined threshold. When the load current falls below a predefined
threshold, the regulator operates in power save mode (PSM),
improving the light load efficiency.
The two bucks operate out of phase to reduce the input capaci-
tor requirement. The low quiescent current, low dropout voltage,
and wide input voltage range of the ADP5034 LDOs extend the
battery life of portable devices. The ADP5034 LDOs maintain
power supply rejection greater than 60 dB for frequencies as
high as 10 kHz while operating with a low headroom voltage.
Regulators in the ADP5034 are activated through dedicated
enable pins. The default output voltages can be externally set in
the adjustable version, or factory programmable to a wide range
of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT
AVIN
HOUSEKEEPING
C
AVIN
VOUT1
0.1µF
VIN1
SW1
C1
FB1
4.7µF
BUCK1
PGND1
ON
EN1
EN1
OFF
MODE
MODE
VOUT2
VIN2
MODE
SW2
C2
4.7µF
BUCK2
FB2
EN2
EN2
PGND2
EN3
VOUT3
EN3
LDO1
FB3
VIN3
(ANALOG)
C3
1µF
EN4
ON
VOUT4
EN4
OFF
LDO2
FB4
VIN4
(DIGITAL)
C4
1µF
ADP5034
AGND
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Dual 3 MHz, 1200 mA Buck
ADP5034
L1 1µH
V
AT
OUT1
1200mA
R1
C5
R2
10µF
PWM
PSM/PWM
L2 1µH
V
AT
OUT2
1200mA
R3
C6
R4
10µF
V
AT
OUT3
300mA
R5
C7
1µF
R6
V
AT
OUT4
300mA
R7
C8
1µF
R8
©2011 Analog Devices, Inc. All rights reserved.
www.analog.com

ADP5034 Summary of contents

  • Page 1

    ... The two bucks operate out of phase to reduce the input capaci- tor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5034 LDOs extend the battery life of portable devices. The ADP5034 LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage ...

  • Page 2

    ... ADP5034 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 General Specifications ................................................................. 3 BUCK1 and BUCK2 Specifications ........................................... 4 LDO1 and LDO2 Specifications ................................................. 4 Input and Output Capacitor, Recommended Specifications .. 5 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ...

  • Page 3

    ... SHUTDOWN J UVLO VIN1RISE UVLO VIN1FALL UVLO VIN1RISE UVLO VIN1FALL to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal level. Start-up AVIN cal Performance Characteristics Rev Page ADP5034 = A Min Typ Max Unit 2.3 5.5 V 150 °C 20 °C 250 μs 300 μ ...

  • Page 4

    ... ADP5034 BUCK1 AND BUCK2 SPECIFICATIONS 2 5 −40°C to +125°C for minimum/maximum specifications, and T AVIN IN1 IN2 J 1 specifications, unless otherwise noted. Table 2. Parameter Symbol OUTPUT CHARACTERISTICS Output Voltage Accuracy OUT1 OUT2 Line Regulation (ΔV /V OUT1 (ΔV /V OUT2 Load Regulation (Δ ...

  • Page 5

    ... OUT3 = 1 OUT4 = 1 OUT4 = 1 OUT4 Min Typ Max 4.7 40 MIN2 7 40 MIN2 0.70 MIN4 0.001 1 ADP5034 Max Unit 0.515 V mV 140 Ω μV rms μV rms Unit μF μF μF Ω ...

  • Page 6

    ... ADP5034 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVIN to AGND VIN1, VIN2 to AVIN PGND1, PGND2 to AGND VIN3, VIN4, VOUT1, VOUT2, FB1, FB2, FB3, FB4, EN1, EN2, EN3, EN4, MODE to AGND VOUT3 to AGND VOUT4 to AGND SW1 to PGND1 SW2 to PGND2 Storage Temperature Range Operating Junction Temperature ...

  • Page 7

    ... TOP VIEW SW2 4 15 SW1 (Not to Scale) PGND2 5 14 PGND1 MODE NOTES CONNECT. DO NOT CONNECT TO THIS PIN RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE GROUND PLANE. Figure 2. Pin Configuration—View from the Top of the Die Rev Page ADP5034 ...

  • Page 8

    ... ADP5034 TYPICAL PERFORMANCE CHARACTERISTICS 3 25°C, unless otherwise noted. IN1 IN2 IN3 IN4 A 140 120 100 2.3 2.8 3.3 3.8 INPUT VOLTAGE (V) Figure 3. System Quiescent Current vs. Input Voltage 1 1 3.3 V, All Channels Unloaded OUT2 OUT3 OUT4 IOUT 2 VOUT CH1 2 ...

  • Page 9

    ... OUT V = 1.8 V, PWM Mode OUT2 100 0.001 0.01 0.1 I (A) OUT V = 0.8 V, Auto Mode OUT1 100 0.001 0.01 0.1 I (A) OUT V = 0.8 V, PWM Mode OUT1 ADP5034 2. ...

  • Page 10

    ... ADP5034 100 +25°C 10 +85°C –40°C 0 0.001 0.01 I (A) OUT Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature 3 3.3 V, Auto Mode IN OUT1 100 +85°C 90 +25° –40° 0.001 0.01 I (A) OUT Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature ...

  • Page 11

    ... CH4 5.00V T 60.000µ from mA, OUT1 V = 3.3 V, Auto Mode OUT1 VOUT 1 I OUT 2 CH1 50.0mV CH2 50.0mA Ω M 20.0µs A CH2 CH4 5.00V 22.20% from mA, OUT2 V = 1.8 V, Auto Mode OUT2 ADP5034 4.80V = 4 5.0 V, 356mA 379mA ...

  • Page 12

    ... ADP5034 VOUT 1 I OUT 2 CH1 50.0mV CH2 200mA Ω M 20.0µs A CH2 CH4 5.00V 20.40% Figure 27. BUCK1 Response to Load Transient 3.3 V, Auto Mode OUT1 VOUT 1 I OUT 2 CH1 100mV CH2 200mA Ω M 20.0µs A CH2 CH4 5.00V ...

  • Page 13

    ... LOAD CURRENT (A) IN3 T I OUT 2 VOUT 1 CH1 100mV CH2 100mA Ω M 40.0µs A CH2 19.20% from mA, OUT3 V = 2.8 V OUT3 T VIN VOUT CH1 20.0mV M 100µs A CH3 CH3 1.00V T 28.40 2.8 V OUT3 ADP5034 0. 2.8 V OUT3 52.0mA 4.80V ...

  • Page 14

    ... ADP5034 3. 0.001 0.01 0 (mA) LOAD Figure 39. LDO Output Noise vs. Load Current, Across Input Voltage 2.8 V OUT3 3. 0.001 0.01 0 (mA) LOAD Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage 3.0 V OUT3 0 100µ ...

  • Page 15

    ... The two bucks operate synchronized to each other. The ADP5034 has individual enable pins (EN1 to EN4) control- ling the activation of each regulator. The regulators are activated by a logic level high applied to the respective EN pin. EN1 controls BUCK1, EN2 controls BUCK2, EN3 controls LDO1, and EN4 controls LDO2 ...

  • Page 16

    ... The ADP5034 has an individual control pin for each regulator. A logic level high applied to the ENx pin activates a regulator, whereas a logic level low turns off a regulator. Figure 46 shows the regulator activation timings for the ADP5034 when all enable pins are connected to AVIN. Also shown is the active pull-down activation. V UVLO ...

  • Page 17

    ... The ADP5034 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. Additionally, the ADP5034 ensures that when both bucks are in PWM mode, they operate out of phase, whereby the Buck2 pFET starts conducting exactly half a clock period after the BUCK1 pFET starts conducting ...

  • Page 18

    ... Figure 46 shows the activation timings for the active pull-downs during regulator activation and deactivation. LDO1 AND LDO2 The ADP5034 contains two LDOs with low quiescent current and low dropout linear regulators, and provides up to 300 mA of output current. Drawing a low 10 μA quiescent current (typical load makes the LDO ideal for battery-operated portable equipment ...

  • Page 19

    ... For the adjustable model, referring to Figure 49 the total combined resistance for R1 and R2 is not to exceed 400 kΩ. Inductor The high switching frequency of the ADP5034 bucks allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 μH and 3 μH. Suggested inductors are shown in Table 8 ...

  • Page 20

    ... VOUT3 EN3 LDO1 FB3 VIN3 (ANALOG) C3 1µF EN4 ON VOUT4 EN4 OFF LDO2 FB4 VIN4 (DIGITAL) C4 1µF ADP5034 AGND Rev Page Data Sheet Case Type Model Size X5R GRM188R60J106 0603 X5R C1608JB0J106K 0603 X5R ECJ1VB0J106M 0603 Case Type Model ...

  • Page 21

    ... ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 μF capacitance with an ESR of 1 Ω or less is recommended to ensure that stability of the ADP5034. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP5034 to large changes in load current ...

  • Page 22

    ... ADP5034 resumes normal operation. This section provides guidelines to calculate the power dissi- pated in the device and ensure that the ADP5034 operates below the maximum allowable junction temperature. The efficiency for each regulator on the ADP5034 is given by P η = × ...

  • Page 23

    ... RISE FALL switching node, SW. For the ADP5034, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimat- ing the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers ...

  • Page 24

    ... ADP5034 PCB LAYOUT GUIDELINES Poor layout can affect ADP5034 performance, causing electro- magnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines. Also, refer to the UG-271 user guide ...

  • Page 25

    ... VIN3 (ANALOG) C3 1µF EN4 ON VOUT4 EN4 OFF LDO2 FB4 VIN4 (DIGITAL) C4 1µF ADP5034 AGND Figure 53. ADP5034 Adjustable Output Voltages with Enable Pins Part Number Vendor JMK105BJ104MV-F Taiyo-Yuden LMK105BJ105MV-F Taiyo-Yuden ECJ-0EB0J475M Panasonic-ECG JMK107BJ106MA-T Taiyo-Yuden BRC1608T1R0M Taiyo-Yuden LQM2MPN1R0NG0B Murata EPL2014-102ML Coilcraft ...

  • Page 26

    ... THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board for ADP5034ACPZ-R7 Evaluation Board for ADP5034ACPZ-2-R7 Package Option CP-24-10 CP-24-10 CP-24-10 ...

  • Page 27

    ... Data Sheet NOTES Rev Page ADP5034 ...

  • Page 28

    ... ADP5034 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09703-0-10/11(A) Rev Page Data Sheet ...