ADP5040 Analog Devices, ADP5040 Datasheet - Page 27

• Manufacturer Part Number: ADP5040
• Description: Micro PMU with 1.2 A Buck Regulator and Two 300 mA LDOs
• Manufacturer: Analog Devices

Data Sheet
The
and PWM operation. A high logic level applied to the MODE
pin forces the buck to operate in PWM mode. A logic level low
sets the buck to operate in auto PSM/PWM.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The buck employs
a scheme that enables this current to remain accurately con-
trolled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to, and exit from, the PSM
mode. The PSM current threshold is optimized for excellent
efficiency over all load currents.
Short-Circuit Protection
The buck includes frequency foldback to prevent current
runaway on a hard short at the output. When the voltage at the
feedback pin falls below half the internal reference voltage,
indicating the possibility of a hard short at the output, the
switching frequency is reduced to half the internal oscillator
frequency. The reduction in the switching frequency allows
more time for the inductor to discharge, preventing a runaway
of output current.
Soft Start
The buck has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter.
Current Limit
The buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the
output. The negative current limit prevents the inductor
current from reversing direction and flowing out of the load.
100% Duty Operation
With a dropping input voltage or with an increase in load
current, the buck may reach a limit where, even with the PFET
ADP5040
has a dedicated MODE pin controlling the PSM
Rev. 0 | Page 27 of 40
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck transitions to a
mode where the PFET switch stays on 100% of the time. When
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.
LDO SECTION
The
that provide output currents up to 300 mA. The low 10 μA
typical quiescent current at no load makes the LDO ideal for
battery-operated portable equipment.
The LDOs operate with an input voltage range of 1.7 V to 5.5 V.
The wide operating range makes these LDOs suitable for
cascade configurations where the LDO supply voltage is
provided from the buck regulator.
Each LDO output voltage is set though external resistor dividers
as shown in Figure 103. V
output voltage can be set from 0.8 V to 5.2 V.
The LDOs also provide high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with small 1 µF ceramic input and output capacitors.
LDO2 is optimized to supply analog circuits because it offers
better noise performance compared to LDO1. LDO1 should be
used in applications where noise performance is not critical.
VIN2, VIN3
ADP5040
Figure 103. LDOs External Output Voltage Setting
contains two LDOs with low quiescent current
LD01, LD02
FB2
VOUT2, VOUT3
FB2, FB3
and V
FB3
R
R
A
B
are internally set to 0.5 V. The
C7
2.2µF
ADP5040
VOUT2,
VOUT3