ADP5041

Manufacturer Part NumberADP5041
DescriptionMicro PMU with 1.2 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset
ManufacturerAnalog Devices
ADP5041 datasheet
 


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Data Sheet
FEATURES
Input voltage range: 2.3 V to 5.5 V
One 1.2 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open-drain processor reset with externally adjustable
threshold monitoring
Guaranteed reset output valid to V
AVIN
Manual reset input
Watchdog refresh input
Buck key specifications
Output voltage range: 0.8 V to 3.8 V
Current mode topology for excellent transient response
3 MHz operating frequency
Peak efficiency up to 96%
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PWM/PSM mode
100% duty cycle low dropout mode
LDOs key specifications
Output voltage range: 0.8 V to 5.2 V
Low input supply voltage from 1.7 V to 5.5 V
Stable with 2.2 μF ceramic output capacitors
High PSRR
Low output noise
Low dropout voltage
−40°C to +125°C junction temperature range
GENERAL DESCRIPTION
The
ADP5041
combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes
board space.
When the MODE pin is set to logic high, the buck regulator
operates in forced PWM mode. When the MODE pin is set to
logic low, the buck regulator operates in PWM mode when the
load is around the nominal value. When the load current falls
below a predefined threshold, the regulator operates in power
save mode (PSM), improving the light load efficiency. The low
quiescent current, low dropout voltage, and wide input voltage
0
R
ev.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Micro PMU with 1.2 A Buck, Two 300 mA LDOs,
Supervisory, Watchdog, and Manual Reset
V
= 2.3V TO
IN1
5.5V
V
= 1.7V
IN2
TO 5.5V
= 1 V
V
= 1.7V
IN3
TO 5.5V
range of the
devices. The
greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.
Each regulator in the
the respective enable pin. The output voltages of the regulators
and the reset threshold are programmed through external resistor
dividers to address a variety of applications. The
contains supervisory circuits that monitor power supply voltage
levels and code execution integrity in microprocessor-based
systems. They also provide power-on reset signals. An on-chip
watchdog timer can reset the microprocessor if it fails to strobe
within a preset timeout period.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
ADP5041
FUNCTIONAL BLOCK DIAGRAM
VOUT1
R
= 30Ω
FILT
AVIN
L1
1µH
SW
FB1
R1
BUCK
VBIAS
R2
VIN1
PGND
C1
4.7µF
EN_BK
ON
FPWM
MODE
EN1
OFF
VOUT2
LDO1
VIN2
(DIGITAL)
R3
FB2
C2
EN_LDO1
1µF
R4
ON
EN2
OFF
nRSTO
VBIAS
MR
WDI
SUPERVISOR
VTHR
ON
EN3
R5
R4
OFF
EN_LDO2
VOUT3
VIN3
LDO2
(ANALOG)
FB3
C3
1µF
R7
R3
AGND
Figure 1.
ADP5041
LDOs extend the battery life of portable
ADP5041
LDOs maintain a power supply rejection
ADP5041
is activated by a high level on
ADP5041
www.analog.com
2011
©
Analog Devices, Inc. All rights reserved.
V
AT
OUT1
1.2A
C6
10µF
PSM/PWM
V
AT
OUT2
300mA
C5
2.2µF
µP
V
AT
OUT3
300mA
C6
2.2µF

ADP5041 Summary of contents

  • Page 1

    ... LDO2 (ANALOG) FB3 C3 1µ AGND Figure 1. ADP5041 LDOs extend the battery life of portable ADP5041 LDOs maintain a power supply rejection ADP5041 is activated by a high level on ADP5041 www.analog.com 2011 © Analog Devices, Inc. All rights reserved OUT1 1.2A C6 10µF PSM/PWM ...

  • Page 2

    ... ADP5041 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 General Specifications ................................................................. 3 Supervisory Specifications .......................................................... 3 Buck Specifications ....................................................................... 4 LDO1, LDO2 Specifications ....................................................... 5 Input and Output Capacitor, Recommended Specifications .. 6 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...

  • Page 3

    ... SINK V AVIN ≥ 4 3.2 mA OL4V5 SINK AVIN = 5.5 V Min Typ Max 0.495 0.500 0.505 160 200 240 80 Rev Page ADP5041 = −40°C to +125°C for minimum/maximum J Min Typ Max 2.275 3.9 1.95 3.1 0.1 2 150 20 250 85 1.2 0.4 0.05 1 0.3 0.3 0.3 0 25°C for typical specifications, ...

  • Page 4

    ... ADP5041 Parameter WATCHDOG INPUT Watchdog Timeout Period Option 0 Option 1 WDI Pulse Width WDI Input Threshold WDI Input Current (Source) WDI Input Current (Sink) MANUAL RESET INPUT MR Input Pulse Width MR G litch Rejection MR Pull-Up Resistance MR to Reset Delay BUCK SPECIFICATIONS AVIN, VIN1 = 2 5 1.8 V ...

  • Page 5

    ... 2 2 ADP5041 1 Unit V µA µA µA µA µ %/ Ω mA µV rms µV rms µV rms µV rms µV rms µV rms ...

  • Page 6

    ... ADP5041 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 5. Parameter INPUT CAPACITANCE (BUCK OUTPUT CAPACITANCE (BUCK) INPUT AND OUTPUT CAPACITANCE 3 (LDO1, LDO2) CAPACITOR ESR 1 The minimum input capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met ...

  • Page 7

    ... V to +0.3 V Table 7. Thermal Resistance −0 +0.3 V −0 (AVIN + 0.3 V) Package Type 20-Lead, 0.5 mm pitch LFCSP −0 (VIN1 + 0.3 V) −65°C to +150°C ESD CAUTION −40°C to +125°C JEDEC J-STD-020 3000 V 1500 V 200 V Rev Page ADP5041 θ θ Unit 4.2 °C/W ...

  • Page 8

    ... WDI Watchdog Refresh Input from Processor. If WDI is in high-Z, watchdog is disabled Manual Reset Input, Active Low. 0 EPAD Exposed Pad (Analog Ground). The exposed pad must be connected to the system ground plane. ADP5041 TOP VIEW (Not to Scale) 15 FB2 FB3 1 VOUT3 2 14 VOUT2 ...

  • Page 9

    ... OUT1 1MΩ B CH1 8.0V/DIV 20.0M A CH1 640mV W 1MΩ B CH2 2.0V/DIV 500.0M W 200mA/DIV 1MΩ B 20.0M CH3 W 1MΩ B CH4 5.0V/DIV 500.0M W Figure 8. Buck Startup 1 OUT1 OUT ADP5041 50µs/DIV 2.0MS/s 500ns/pt 50µs/DIV 2.0MS/s 500ns/pt 50µs/DIV 2.0MS/s 500ns/pt ...

  • Page 10

    ... ADP5041 3.90 3.88 3.86 3.84 3.82 3.80 3.78 3.76 3.74 3.72 3.70 0.01 0.1 OUTPUT CURRENT (A) Figure 9. Buck Load Regulation Across Temperature, V Auto Mode 3.39 3.37 3.35 3.33 3.31 3.29 3.27 3.25 0.01 0.1 OUTPUT CURRENT (A) Figure 10. Buck Load Regulation Across Temperature, V Auto Mode 1.820 1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 0.01 0.1 OUTPUT CURRENT (A) Figure 11. Buck Load Regulation Across Temperature, V Auto Mode 1.24 1.23 1.22 1.21 1.20 1.19 –40°C +25° ...

  • Page 11

    ... OUTPUT CURRENT ( 3.8 V, PWM Mode OUT1 0.0001 0.001 0.01 0.1 OUTPUT CURRENT ( 3.3 V, Auto Mode OUT1 0.001 0.01 0.1 OUTPUT CURRENT ( 3.3 V, PWM Mode OUT1 ADP5041 ...

  • Page 12

    ... ADP5041 100 0.0001 0.001 0.01 OUTPUT CURRENT (A) Figure 21. Buck Efficiency vs. Load Current, Across Input Voltage 1.8 V, Auto Mode OUT1 100 0.001 0.01 0.1 OUTPUT CURRENT (A) Figure 22. Buck Efficiency vs. Load Current, Across Input Voltage 1.8 V, PWM Mode ...

  • Page 13

    ... Rev Page 0.001 0.01 0.1 OUTPUT CURRENT ( 5 1.2 V, PWM Mode IN OUT1 V = 3.3V OUT 0 3.4 3.9 4.4 4.9 V (V) IN Figure 31. Buck DC Current Capability vs. Input Voltage V = 1.8V OUT 0 2.4 2.9 3.4 3.9 4.4 V (V) IN Figure 32. Buck DC Current Capability vs. Input Voltage ADP5041 –40°C +25°C +85°C 1 5.4 4.9 5.4 ...

  • Page 14

    ... ADP5041 2 1.2V 1.8 OUT 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.4 2.9 3.4 3.9 4.4 V (V) IN Figure 33. Buck DC Current Capability vs. Input Voltage 2.94 2.92 2.90 2.88 2.86 2.84 2.82 2.80 0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) Figure 34. Buck Switching Frequency vs. Output Current, Across Temperature 1.8 V, PWM Mode OUT1 4 V OUT 200mA/DIV 1MΩ B CH2 20.0M A CH1 W 1MΩ B CH3 3.0V/DIV 20.0M W CH4 40.0mV/DIV 20.0M Figure 35. Typical Waveforms ...

  • Page 15

    ... mA, Auto Mode OUT1 OUT1 OUT SW B CH1 3.0V/DIV A CH3 4.48V 400M W CH2 B 50.0mV/DIV 20.0M W 1MΩ B CH3 1.0V/DIV 20. 3.3 V, PWM Mode OUT1 ADP5041 200µs/DIV 1.0MS/s 1.0µs/pt 200µs/DIV 1.0MS/s 1.0µs/pt 200µs/DIV 1.0MS/s 1.0µs/pt ...

  • Page 16

    ... ADP5041 OUT CH1 3.0V/DIV 400M A CH3 W B CH2 20.0mV/DIV 20.0M W 1MΩ B 1.0V/DIV 20.0M CH3 W Figure 45. Buck Response to Line Transient, Input Voltage from 4 5 1.8 V, PWM Mode OUT1 OUT CH1 3.0V/DIV 20.0M A CH3 W CH2 B 50.0mV/DIV 20.0M W 1MΩ B CH3 1 ...

  • Page 17

    ... V, PWM Mode OUT1 SW V OUT I OUT 1MΩ B CH1 4.0V/DIV 20.0M A CH3 150mA W B CH2 100mV/DIV 20.0M W 1MΩ B 20.0M CH3 300mA/DIV 500 mA, OUT1 V = 1.8 V, PWM Mode OUT1 ADP5041 500µs/DIV 20.0MS/s 50.0ns/pt 500µs/DIV 20.0MS/s 50.0ns/pt 500µs/DIV 20.0MS/s 50.0ns/pt ...

  • Page 18

    ... ADP5041 OUT 2 I OUT 3 B CH1 4.0V/DIV 20.0M A CH3 W B CH2 50.0mV/DIV 20.0M W 1MΩ B 100mA/DIV 120.0M CH3 W Figure 57. Buck Response to Load Transient 1.2 V, PWM Mode OUT1 OUT 2 I OUT 3 CH1 4.0V/DIV 20.0M A CH3 CH2 50.0mV/DIV 20.0M 1MΩ B CH3 200mA/DIV 20.0M W Figure 58. Buck Response to Load Transient ...

  • Page 19

    ... Figure 67. LDO1, LDO2 Load Regulation Across Temperature 3.3 V OUT 1.800 3.6V 4.5V 5.5V 1.795 2.8V 1.790 1.785 1.780 1.775 1.770 0.1 0.001 = 1.8 V Figure 68. LDO1, LDO2 Load Regulation Across Temperature, V OUT Rev Page ADP5041 3.6V 4.5V 5.5V 2.8V 0.01 0.1 OUTPUT CURRENT (A) = 1.2 V OUT –40°C +25°C +85°C 0.01 0.1 OUTPUT CURRENT ( 3.3 V OUT – ...

  • Page 20

    ... ADP5041 1.220 1.215 1.210 1.205 1.200 1.195 1.190 1.185 1.180 0.001 0.01 OUTPUT CURRENT (A) Figure 69. LDO1, LDO2 Load Regulation Across Temperature 1.2 V OUT 4.75 100µA 1mA 10mA 4.73 100mA 200mA 4.71 4.69 4.67 4.65 5.0 5.1 5.2 5.3 INPUT VOLTAGE (V) Figure 70. LDO1, LDO2 Line Regulation Across Input Voltage, V 3.310 100µA 1mA 3 ...

  • Page 21

    ... OUT 200 mA 3.3 V OUT V OUT I OUT B CH2 30.0mV/DIV 20.0M A CH3 89.6mA W 1MΩ B CH3 120M 80.0mA/DIV W OUT 80 mA 1.8 V OUT ADP5041 200µs/DIV 500kS/s 2.0µs/pt from 200µs/DIV 500kS/s 2.0µs/pt from 200µs/DIV 500kS/s 2.0µs/pt from ...

  • Page 22

    ... ADP5041 V OUT 2 I OUT 3 B CH2 50.0mV/DIV 20.0M A CH3 W 1MΩ B CH3 120M 80.0mA/DIV W Figure 81. LDO1, LDO2 Response to Load Transient, I 200 mA 1.8 V OUT V OUT 2 I OUT 3 B CH2 30.0mV/DIV 20.0M A CH3 W 1MΩ B CH3 20.0M 80.0mA/DIV W Figure 82. LDO1, LDO2 Response to Load Transient mA 1.2 V ...

  • Page 23

    ... I OUT2 IN2 LOAD V = 1.5V 1.8V, I OUT2 IN2 LOAD V = 2.8V 3.1V, I OUT2 IN2 LOAD 10 10 100 1k 10k 100k FREQUENCY (Hz) Figure 92. LDO1 Noise Spectrum Across Output Voltage 0 OUT ADP5041 = 3. 3. 1.8V IN 100 3. 3. 1.8V IN 100 1k = 300mA = 300mA = 300mA 1M 10M ...

  • Page 24

    ... ADP5041 100 V = 3.3V 3.6V, I OUT3 IN3 V = 1.5V 1.8V, I OUT3 IN3 V = 2.8V 3.1V, I OUT3 IN3 10 1 0.1 0. 100 1k 10k FREQUENCY (Hz) Figure 93. LDO2 Noise Spectrum Across Output Voltage 0 OUT 100 V = 3.3V 3.6V, I OUT2 IN2 V = 3.3V 3.6V, I OUT3 IN3 V = 1.5V 1.8V, I OUT2 IN2 10 1.0 0 1.5V 1.8V 300mA OUT3 IN3 ...

  • Page 25

    ... 1.5 V IN2 OUT2 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 10 1M 10M Rev Page ADP5041 1mA 10mA 100mA 200mA 300mA 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 100. LDO1 PSRR Across Output Load 1 1.5 V IN2 OUT2 10M ...

  • Page 26

    ... ADP5041 POWER MANAGEMENT UNIT The is a micro power management unit (micro PMU) ADP5041 combing one step-down (buck) dc-to-dc regulator, two low dropout linear regulators (LDOs), and a supervisory circuit, with watchdog, for processor control. The high switching frequency and tiny 20-pin LFCSP package allow for a small power management solution ...

  • Page 27

    ... PSM current threshold. The ADP5041 and PWM operation. A high logic level applied to the MODE pin forces the buck to operate in PWM mode. A logic level low sets the buck to operate in auto PSM/PWM. Rev Page ADP5041 VOUT1 L1 – 1µH SW VOUT1 BUCK R1 ...

  • Page 28

    ... Reset Output The ADP5041 has an active low, open-drain reset output. This output structure requires an external pull-up resistor to connect the reset output to a voltage rail that is no higher than 6 V. The ...

  • Page 29

    ... When reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts. The watchdog timer can be disabled by leaving WDI floating or by three-stating the WDI driver. The ADP5041 watchdog timer values as indicated in Table 18. V SENSED nRSTO WDI Rev ...

  • Page 30

    ... REGULATORS AND SUPERVISORY NOT ACTIVATED END OF POR STANDBY ALL ENx = LOW ENx = HIGH ACTIVE WDOG1 TIMEOUT VMON < VTH RESET NORMAL ADP5041 Figure 107. State Flow Rev Page AVIN < VUVLO ALL REGULATORS AND SUPERVISORS ACTIVATED END OF RESET PULSE ( Data Sheet ...

  • Page 31

    ... The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: V RIPPLE Rev Page ADP5041 × (1 − TEMPCO) × (1 − TOL) OUT BIAS VOLTAGE (V) Figure 108. Typical Capacitor Performance ...

  • Page 32

    ... The maximum value not to exceed 200 kΩ (see Figure 103). OUTPUT CAPACITOR The ADP5041 space-saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 µ ...

  • Page 33

    ... V, as shown in Figure 110. BIAS = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.72 μF EFF ADP5041 is equipped with glitch rejection circuitry. The typical , transient duration vs. the transient magnitude 0 COMPARATOR OVERDRIVE (% OF V Figure 111. Maximum V Transient Duration vs. Reset TH Threshold Overdrive ADP5041 , it is imperative 100 ) TH ...

  • Page 34

    ... Equation 8 to Equation 11 and the losses in the LDOs provided ADP5041 by Equation 12. Buck Regulator Power Dissipation ADP5041 The power loss of the buck regulator is approximated by operates ADP5041 where: P DBUCK P is the inductor power losses. L The inductor losses are external to the device and they do not have any effect on the die temperature ...

  • Page 35

    ... D JA value for the 20-lead × LFCSP based on a 4-layer, 4 inch × 3 inch, 2.5 oz copper × θ ADP5041 ) due to the losses of all channels by using D , can be estimated using Equation 14. J ADP5041 ) (12) (13) and P using A D (14) ...

  • Page 36

    ... ADP5041 The reliable operation of the buck regulator and the LDO regulator can be achieved only if the estimated die junction temperature of the ADP5041 (Equation 14) is less than 125°C. Reliability and mean time between failures (MTBF) is highly APPLICATION DIAGRAM 2.3V IN1 TO 5.5V 4.7µF OFF ...

  • Page 37

    ... GPL GPL AGND SW GPL GPL PGND ADP5041 EN1 C2 – 1µF 10V/XR5 0402 VOUT2 PPL Figure 114. Suggested Board Layout Rev Page ADP5041 6.0 6.5 7 – 2.2µF 6.3V/XR5 0402 MR WDI VTHR MODE EN2 VIAS LEGEND: PPL = POWER PLANE (+4V) GPL = GROUND PLANE C5 – 2.2µF 6 ...

  • Page 38

    ... PMU Part Number Vendor JMK107BJ475 Taiyo-Yuden LMK105BJ105MV-F Taiyo-Yuden JMK107BJ106MA-T Taiyo-Yuden JMK105BJ225MV-F Taiyo-Yuden LQM2MPN1R0NG0B Murata MDT2520-CN Toko XPL2010-1102ML Coilcraft ADP5041 Analog Devices Rev Page Data Sheet Package 0603 0402 0603 0402 2.0 × 1.6 × 0.9 (mm) 2.5 × 2.0 × 1.2 (mm) 1.9 × 2.0 × 1.0 (mm) 20-Lead LFCSP ...

  • Page 39

    ... Option 1 3.10 Table 17. Reset Timeout Options Options Min Option 0 24 Option 1 160 Table 18. Watchdog Timer Options Selection Min Option 0 81.6 Option 1 1.28 Typ Max 2.15 2.275 3.65 3.90 Typ Max 30 36 200 240 Typ Max 102 122.4 1.6 1.92 Rev Page ADP5041 Unit V V Unit ms ms Unit ms sec ...

  • Page 40

    ... Model Settings ADP5041ACPZ-1- 1.6 sec OUT Min reset t = 160 ms OUT V = 2.15 V UVLO Discharge resistors enabled ADP5041CP-1-EVALZ RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09652-0-12/11(0) 4.10 0.30 4.00 SQ 0.25 3.90 0.20 16 0.50 15 BSC ...