ADP5041 Analog Devices, ADP5041 Datasheet - Page 37

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ADP5041

Manufacturer Part Number
ADP5041
Description
Micro PMU with 1.2 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset
Manufacturer
Analog Devices
Datasheet
Data Sheet
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
PCB LAYOUT GUIDELINES
Poor layout can affect
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
mm
VOUT1
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
0.5
L1 – 1µH
0603
R
1.0
0402
30Ω
FILT
C4 – 10µF
6.3V/XR5
0603
ADP5041
1.5
GPL
PPL
10V/XR5 0603
GPL
C1 – 4.7µF
2.0
performance, causing electro-
PPL
2.5
PPL
3.0
PGND
AVIN
VIN 1
EN1
SW
3.5
Figure 114. Suggested Board Layout
Rev. 0 | Page 37 of 40
4.0
C3 – 1µF
10V/XR5
C2 – 1µF
10V/XR5
0402
0402
GPL
GPL
4.5
ADP5041
AGND
SUGGESTED LAYOUT
See Figure 114 for an example layout.
PPL
PPL
5.0
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
Maximize the size of ground metal on the component side
to help with thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
VOUT2
VOUT3
GPL
GPL
5.5
C6 – 2.2µF
C5 – 2.2µF
6.3V/XR5
6.3V/XR5
0402
0402
6.0
6.5
VTHR
MODE
WDI
EN2
MR
7.0
VIAS LEGEND:
PPL = POWER PLANE (+4V)
GPL = GROUND PLANE
mm
TOP LAYER
2ND LAYER
ADP5041

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