ADP5042

Manufacturer Part NumberADP5042
DescriptionMicro PMU with 0.8 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset
ManufacturerAnalog Devices
ADP5042 datasheet
 


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Data Sheet
FEATURES
Input voltage range: 2.3 V to 5.5 V
One 0.8 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: ±1%
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open drain processor reset with threshold monitoring
±1.5% threshold accuracy over the full temperate range
Guaranteed reset output valid to V
= 1 V
CC
Dual watchdog for secure systems
Watchdog 1 controls reset
Watchdog 2 controls reset and regulators power cycle
Buck key specifications
Current mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100% duty cycle low dropout mode
LDOs key specifications
Low V
from 1.7 V to 5.5 V
IN
Stable with1 µF ceramic output capacitors
High PSRR, 60 dB PSRR up to 1 kHz/10 kHz
Low output noise
110 µV rms typical output noise at V
Low dropout voltage: 150 mV at 300 mA load
−40°C to +125°C junction temperature range
GENERAL DESCRIPTION
The ADP5042 combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes the
board space.
The MODE pin selects the buck mode of operation. When set
to logic high, the buck regulators operate in forced PWM mode.
When the MODE pin is set to logic low, the buck regulators
operate in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold
the regulator operates in power save mode (PSM) improving
the light-load efficiency.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Micro PMU with 0.8 A Buck, Two 300 mA LDOs
Supervisory, Watchdog and Manual Reset
VIN1 = 2.3V
TO 5.5V
4.7µF
VIN2 = 1.7V
TO 5.5V
VIN3 = 1.7V
TO 5.5V
= 2.8 V
OUT
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5042 LDOs extend the battery life of
portable devices. The two LDOs maintain power supply
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
Each regulator is activated by a high level on the respective
enable pin. The ADP5042 is available with factory programmable
default output voltages and can be set to a wide range of options.
The ADP5042 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. They also provide power-on
reset signals. An on-chip dual watchdog timer can reset the
microprocessor or power cycle the system (Watchdog 2) if it
fails to strobe within a preset timeout period.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
ADP5042
HIGH LEVEL BLOCK DIAGRAM
= 30Ω
R
FILT
AVIN
1µH
AVIN
SW
VOUT1
VIN1
BUCK
C5
PGND
EN_BK
ON
FPWM
MODE
EN1
OFF
VOUT2
LDO1
VIN2
(DIGITAL)
C1
EN_LDO1
1µF
ON
WSTAT
EN2
OFF
AVIN
nRSTO
WDI1
MR
WDI2
ON
EN3
OFF
EN_LDO2
VOUT3
VIN3
LDO2
(ANALOG)
C3
1µF
AGND
Figure 1.
www.analog.com
©2010-2011 Analog Devices, Inc. All rights reserved.
L1
V
AT
OUT1
800mA
C6
10µF
PSM/PWM
V
AT
OUT2
300mA
C2
1µF
V
AT
OUT3
300mA
C4
1µF

ADP5042 Summary of contents

  • Page 1

    ... V OUT The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5042 LDOs extend the battery life of portable devices. The two LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. ...

  • Page 2

    ... ADP5042 TABLE OF CONTENTS Features .............................................................................................. 1 High Level Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 General Specification ................................................................... 3 Supervisory Specification ............................................................ 3 Buck Specifications ....................................................................... 5 LDO1, LDO2 Specifications ....................................................... 5 Input and Output Capacitor, Recommended Specifications .. 6 Absolute Maximum Ratings ............................................................ 7 Thermal Data ................................................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Theory of Operation ...

  • Page 3

    ... RP2 3 150 ) 2 D2 81.6 102 122.4 1.28 1.6 1.92 Rev Page ADP5042 = 25°C, unless otherwise noted. Regulators A Min Typ 1.95 0.1 150 20 1.2 0. Unit Test Conditions/Comments µA AVIN = 5.5 V, EN1 = EN2 = EN3 = VIN µA AVIN = 3.6 V, EN1 = EN2 = EN3 = VIN 25°C, sensed on VOUTx ...

  • Page 4

    ... ADP5042 Parameter Watchdog 2 Timeout Period (t ) WD2 Option A Option B Option C Option D Option E Option F Option G Option H Watchdog 2 Power Off Period (t ) POFF Option A Option B WDI1 Pulse Width WDI2 Pulse Width Watchdog Status Timeout Period (t WDCLEAR WDI1 Input Current (Source) WDI1 Input Current (Sink) WDI2 Internal Pull-Down ...

  • Page 5

    ... C OUT IN Min Typ 1 −40°C to +125°C 67 100 −1 −2 −3 −0.03 ADP5042 = 25°C A Max Unit 5 μA 1.0 μA 240 mΩ 190 mΩ 235 mΩ 210 mΩ 1600 mA Ω ...

  • Page 6

    ... ADP5042 Parameter Symbol Load Regulation 1 ∆V ∆V DROPOUT VOLTAGE 2 V ACTIVE PULL-DOWN R START-UP TIME T CURRENT-LIMIT THRESHOLD 3 I LIMIT OUTPUT NOISE OUT OUT POWER SUPPLY REJECTION RATIO PSRR 1 Based on an end-point calculation using 1 mA and 100 mA loads. 2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2 ...

  • Page 7

    ... THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP5042 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated ...

  • Page 8

    ... Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled. 20 Manual Reset Input, Active Low AGND Analog Ground (TP = Thermal Pad). Exposed pad should be connected to AGND. 15 WSTAT NC 1 VOUT3 2 14 VOUT2 ADP5042 VIN3 3 13 VIN2 TOP VIEW EN3 4 12 WDI2 (Not to Scale) nRSTO 5 11 VOUT1 NOTES 1 ...

  • Page 9

    ... CH3 20.0M W 5.0V/DIV 1MΩ B CH4 500M W Figure 6. Buck Startup, VOUT1 = 1 OUT2 3.34 3.32 3.30 3.28 3.26 3.24 3.22 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 OUTPUT CURRENT (A) 1.830 1.825 1.820 1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 1.775 0 0.1 0.2 0.3 0.4 0.5 OUTPUT CURRENT (A) ADP5042 50µs/DIV 20.0MS/s 50.0ns/ –40°C +25°C +85°C 0.8 0.9 1.0 –40°C +25°C +85°C 0.6 0.7 0.8 ...

  • Page 10

    ... ADP5042 1.795 1.794 +85°C 1.793 1.792 +25°C 1.791 1.790 1.789 1.788 1.787 1.786 –40°C 1.785 1.784 0 0.1 0.2 0.3 0.4 OUTPUT CURRENT (A) Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode 1.797 1.796 1.795 VIN = 5.5V 1.794 VIN = 4.5V 1.793 VIN = 3.6V 1.792 1.791 1.790 0 0.1 0.2 0.3 0.4 OUTPUT CURRENT (A) Figure 10 ...

  • Page 11

    ... Figure 20. Typical Waveforms, VOUT1 = 3 Rev Page 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 2.6 3.6 4.6 INPUT VOLTAGE (V) 3.10 –40°C 3.05 +25°C 3.00 2.95 +85°C 2.90 2.85 0 0.1 0.2 0.3 0.4 0.5 0.6 OUTPUT CURRENT (A) VOUT1 = 1.8 V, PWM Mode VOUT CH1 20.0mV/DIV 20.0M A CH1 2.4mV W 200mA/DIV 1MΩ B CH2 20.0M W 1MΩ B CH3 2.0V/DIV 20. mA, Auto Mode OUT1 ADP5042 5.6 0.7 0.8 5.0µs/DIV 20.0MS/s 50.0ns/pt ...

  • Page 12

    ... ADP5042 VOUT 2.0V/DIV 1MΩ B CH1 20.0M A CH1 W B CH2 50.0mV/DIV 20. CH3 500mA/DIV 20.0M W Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT2 = 30 mA, Auto Mode VOUT 2.0V/DIV 1MΩ B CH1 20.0M A CH1 W B CH2 50.0mV/DIV 20. CH3 500mA/DIV 20.0M W Figure 22. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode ...

  • Page 13

    ... Figure 30. LDO1 Startup, VOUT3=1.5 V, IOUT3 = 5 mA IIN VOUT EN B CH1 1V/DIV 1MΩ 500M A CH2 1.14V W B CH2 3V/DIV 1MΩ 500M W B CH3 50mA/DIV 1MΩ 20.0M W Figure 31. LDO2 Startup, VOUT3=3.3 V, IOUT3 = 5 mA 3.3V 4.5V 5.0V 5.5V 0.0001 0.001 0.01 OUTPUT CURRENT (A) ADP5042 50µs/DIV 2MS/s 500ns/pt 100µs/DIV 1MS/s 1.0µs/pt 0.1 ...

  • Page 14

    ... ADP5042 1.53 +85°C +25°C –40°C 1.52 1.51 1.5 1.49 1.48 1.47 0.0001 0.001 0.01 OUTPUT CURRENT (A) Figure 33. LDO1 Load Regulation Across Temperature, VIN2 = 3.3 V, VOUT2 = 1.5 V 1.520 100µA 1mA 10mA 1.515 100mA 150mA 1.510 1.505 1.500 1.495 1.490 1.485 1.480 3.6 4.5 INPUT VOLTAGE (V) Figure 34. LDO1 Line Regulation Across Output Load, VOUT2 = 1 ...

  • Page 15

    ... Figure 44. LDO1, LDO2 Output Current Capability vs. Input Voltage Rev Page VIN VOUT B 20.0M CH1 10.0mV/DIV A CH2 W 1MΩ B CH2 800mV/DIV 20.0M W VOUT3 = 3.3 V VIN VOUT 20.0M CH1 10.0mV/Div A CH2 W 1MΩ B 20.0M CH2 800mV/Div W 0.1 0.2 0.3 0.4 0.5 0.6 LOAD CURRENT (A) ADP5042 5.33V 5.33V 5.5V 4.5V 3.6V 0.7 0.8 ...

  • Page 16

    ... ADP5042 100 CH2; V CH2; V CH2; V CH2; V CH2 0.0001 0.001 0.01 0.1 LOAD (mA) Figure 45. LDO1 Output Noise vs. Load Current, Across Input and Output Voltage 100 CH3; VOUT = 3.3V; VIN = 5V CH3; VOUT = 3.3V; VIN = 3.6V CH3; VOUT = 2.8V; VIN = 3.1V CH3; VOUT = 1.5V; VIN = 5V CH3; VOUT = 1.5V; VIN = 1.8V 10 0.0001 0.001 0.01 0.1 LOAD (mA) Figure 46 ...

  • Page 17

    ... FREQUENCY (Hz) –10 1mA 10mA –20 100mA 200mA –30 300mA –40 –50 –60 –70 –80 –90 –100 10 100 1k 10k 100k FREQUENCY (Hz) ADP5042 1M 10M 1M 10M ...

  • Page 18

    ... VDDA OPMODE_FUSES ADP5042 POWER MANAGEMENT UNIT The ADP5042 is a micro power management unit (micro PMU) combing one step-down (buck) dc-to-dc convertor, two low dropout linear regulators (LDOs), and a supervisory circuit, with dual watchdog, for processor control. The regulators are activated by a logic level high applied to the respective EN pin. The EN1 controls the buck regulator, the EN2 controls LDO1, and the EN3 controls LDO2 ...

  • Page 19

    ... V typical. Enable/Shutdown The ADP5042 has individual control pins for each regulator. A logic level high applied to the ENx pin activates a regulator, a logic level low turns off a regulator. When regulators are turned off after a Watchdog 2 event (see the Watchdog 2 Input section), the reactivation of the regulator occurs with a factory programmed order (see Table 9) ...

  • Page 20

    ... Manual Reset Input The ADP5042 features a manual reset input ( MR ) which, when driven low, asserts the reset output. When MR transitions from low to high, reset remains asserted for the duration of the reset active timeout period before deasserting. The MR input has a 52 kΩ ...

  • Page 21

    ... Data Sheet Watchdog 1 Input The ADP5042 features a watchdog timer that monitors micro- processor activity. A timer circuit is cleared with every low-to- high or high-to-low logic transition on the watchdog input pin (WDI1), which detects pulses as short as 80 ns. If the timer counts through the preset watchdog timeout period (t is asserted ...

  • Page 22

    ... ADP5042 Watchdog Status Indicator In addition to the dual watchdog function, the ADP5042 features a watchdog status monitor available on the WSTAT pin. This pin can be queried by the external processor to determine the origin of a reset. WSTAT is an open-drain output. WSTAT outputs a logic level depending on the condition that has generated a reset ...

  • Page 23

    ... Figure 66. Inductor The high switching frequency of the ADP5042 buck allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 μH and 3 μH. Suggested inductors are shown in Table 11. ...

  • Page 24

    ... The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended to ensure stability of the ADP5042. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP5042 to large changes in load current ...

  • Page 25

    ... Negative-Going V To avoid unnecessary resets caused by fast power supply transients, the ADP5042 is equipped with glitch rejection circuitry. The typical performance characteristic in Figure 64 plots the monitored rail voltage, V The curve shows combinations of transient magnitude and duration for which a reset is not generated for a 2 ...

  • Page 26

    ... Watchdog 1 is kept refreshed or environmental conditions that may unset or damage the processor port controlling the WDI1 pin. In the event of a Watchdog 2 timeout, the ADP5042 power cycles all the supplied rails to guarantee a clean processor start. PCB LAYOUT GUIDELINES ...

  • Page 27

    ... C2 1µF TP11 TP9 TP10 WDI1 TP7 WDI2 TP3 VOUT3 AT 300mA C4 1µF 5.5 6.0 6.5 7.0 mm 3.3V C4 – 1µF 6.3V/XR5 0402 PIN 1 MR WDI1 WMOD NC EN2 VIAs LEGEND PPL = POWER PLANE (+4V) GPL = GROUND PLANE C2 – 1µF 10V/XR5 TOP LAYER 0402 SECOND LAYER 1.5V ADP5042 ...

  • Page 28

    ... FILT L1 1 µH, 0.09 Ω, 290 mA 1 µH, 0.08 Ω, 230 mA IC1 3-regulator micro PMU APPLICATION DIAGRAM V IN1 = 2.3V TO 5.5V VIN2 = 1.7V TO 5.5V PUSH-BUTTON VIN3 = 1.7V TO 5.5V Part Number LMK105BJ105MV-F LMK107BJ475MA-T JMK107BJ106MA-T BRC1608T1R0M GLFR1608T1R0M-LR ADP5042 AVIN R FILT 30Ω AVIN VOUT1 11 BUCK VIN1 PGND 7 9 EN_BK C5 4.7µF MODE ON ...

  • Page 29

    ... Typ Max 200 280 400 560 Monitored Rail VOUT1 pin VOUT2 pin VOUT3 pin AVIN 1 pin Rev Page ADP5042 T = −40°C to +85°C A Min Max Unit 4.700 V 3.003 3.157 V 2.857 3.000 V 2.564 2.696 V 2.438 2.563 V 2.385 V 2.099 V 1 ...

  • Page 30

    ... Regulator Settings ADP5042ACPZ-1-R7 VOUT1 = 1.8 V VOUT2 = 1.5 V VOUT3 = 3.3 V UVLO = 2.2 V Sequencing: LDO1, LDO2, buck ADP5042ACPZ-2-R7 VOUT1 = 1.5 V VOUT2 = 1.8 V VOUT3 = 3.3 V UVLO = 2.2 V Sequencing: LDO1, LDO2, buck ADP5042CP-1-EVALZ ADP5042CP-2-EVALZ RoHS Compliant Part. 2 Monitoring ambient temperature does not guarantee that the junction temperature (T 4.10 0.30 4.00 SQ 0.25 3.90 0.20 16 0.50 15 BSC EXPOSED ...

  • Page 31

    ... Data Sheet NOTES Rev Page ADP5042 ...

  • Page 32

    ... ADP5042 NOTES ©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08811-0-11/11(A) Rev Page Data Sheet ...