ADP5042 Analog Devices, ADP5042 Datasheet - Page 25

• Manufacturer Part Number: ADP5042
• Description: Micro PMU with 0.8 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset
• Manufacturer: Analog Devices

Data Sheet
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5042 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary tempe-
rature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.
Figure 63 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C tempera-
ture range and is not a function of package or voltage rating.
Use the following equation to determine the worst-case capa-
citance accounting for capacitor variation over temperature,
component tolerance, and voltage.
where:
C
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C
Substituting these values into the following equation yields:
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
BIAS
C
C
is the effective capacitance at the operating voltage.
EFF
EFF
1.2
1.0
0.8
0.6
0.4
0.2
0
0
= C
= 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Figure 63. Capacitance vs. Voltage Characteristic
BIAS
× (1 − TEMPCO) × (1 − TOL)
BIAS
1
is 0.94 μF at 1.8 V as shown in Figure 63.
DC BIAS VOLTAGE (V)
2
3
4
5
6
Rev. A | Page 25 of 32
To guarantee the performance of the ADP5042, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
SUPERVISORY SECTION
Watchdog 1 Input Current
To minimize watchdog input current (and minimize overall
power consumption), leave WDI1 low for the majority of the
watchdog timeout period. When driven high, WDI1 can draw
as much as 25 µA. Pulsing WDI1 low-to-high-to-low at a low
duty cycle reduces the effect of the large input current. When
WDI1 is unconnected and WMOD is set to logic level low, a
window comparator disconnects the watchdog timer from the
reset output circuitry so that reset is not asserted when the
watchdog timer times out.
Negative-Going V
To avoid unnecessary resets caused by fast power supply transients,
the ADP5042 is equipped with glitch rejection circuitry. The typical
performance characteristic in Figure 64 plots the monitored rail
voltage, V
The curve shows combinations of transient magnitude and
duration for which a reset is not generated for a 2.93 V reset
threshold part. For example, with the 2.93 V threshold, a
transient that goes 100 mV below the threshold and lasts 8 µs
typically does not cause a reset, but if the transient is any larger
in magnitude or duration, a reset is generated.
Watchdog Software Considerations
In implementing the watchdog strobe code of the micro-
processor, quickly switching WDI1 low to high and then high
to low (minimizing WDI1 high time) is desirable for current
consumption reasons. However, a more effective way of using
the watchdog function can be considered.
A low-to-high-to-low WDI1 pulse within a given subroutine
prevents the watchdog from timing out. However, if the sub-
routine becomes stuck in an infinite loop, the watchdog cannot
detect this because the subroutine continues to toggle WDI1. A
more effective coding scheme for detecting this error involves
1000
900
800
700
600
500
400
300
200
100
0
0.1
TH
Figure 64. Maximum V
, transient duration vs. the transient magnitude.
COMPARATOR OVERDRIVE (% OF V
CC
Transients
Threshold Overdrive
1
TH
Transient Duration vs. Reset
10
TH
)
ADP5042
100