ADP5042

Manufacturer Part NumberADP5042
DescriptionMicro PMU with 0.8 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset
ManufacturerAnalog Devices
ADP5042 datasheet
 


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ADP5042
Watchdog Status Indicator
In addition to the dual watchdog function, the ADP5042
features a watchdog status monitor available on the WSTAT pin.
This pin can be queried by the external processor to determine
the origin of a reset. WSTAT is an open-drain output.
WSTAT outputs a logic level depending on the condition that
has generated a reset. WSTAT is forced low if the reset was
generated because of a Watchdog 2 timeout. WSTAT is pulled
high, through external pull-up, for any other reset cause (Watchdog
1 timeout, power failure or monitored voltage below threshold).
The status monitor is automatically cleared (set to logic level
high) 10 seconds after the nRSTO low to high transition (t
processor firmware must be designed being able to read the
WSTAT flag before t
expiration after a Watchdog 2 reset.
WDCLEAR
The WSTAT flag is not updated in the event of a reset due to a
low voltage threshold detection or Watchdog 1 event occurring
within 10 seconds after nRSTO low to high transition. In this
TRANSITION
STATE
AVIN < VUVLO
TRANSITION
STATE
WDOG1 TIMEOUT
(t
WD1
WSTAT TIMEOUT
TRANSITION
STATE
situation, WSTAT maintains the previous state (see state flow in
Figure 60).
The external processor can further distinguish a reset caused by
a Watchdog 1 timeout from a power failure, status monitor
WSTAT indicating a high level, by implementing a RAM check
or signature verification after reset. A RAM check or signature
failure indicates that a power failure has occurred, whereas a
RAM check or signature validation indicates that a Watchdog 1
timeout has occurred.
Table 10 shows the possible watchdog decoded statuses.
Table 10. Watchdog Status Decoding
),
WDCLEAR
WSTAT
High
High
Low
NO POWER APPLIED TO AVIN.
ALL REGULATORS AND SUPERVISORY
TURNED OFF
NO POWER
AVIN > VUVLO
AVIN < VUVLO
POR
INTERNAL CIRCUIT BIASED
REGULATORS AND
SUPERVISORY NOT ACTIVATED
END OF POR
STANDBY
ALL ENx = HIGH
ALL ENx = LOW
WSTAT
WDOG2
TIMEOUT
TIMEOUT
WSTAT = HIGH
(t
)
(t
)
WDCLEAR
WD2
WSTAT = 1
ALL REGULATORS AND
ACTIVE
SUPERVISOR ACTIVATED
) AND
WDOG1 TIMEOUT
END OF RESET
PULSE (t
(t
)
WD1
WSTAT = HIGH
VMON < VTH
WSTAT = 1
RESET
NORMAL
Figure 60. ADP5042 State Flow
Rev. A | Page 22 of 32
Data Sheet
RAM CHECKSUM
RESET ORIGIN
Failed
Power failure
Ok
Watchdog 1
Don't care
Watchdog 2
AVIN < VUVLO
AVIN < VUVLO
TRANSITION
STATE
WSTAT = 0
WSTAT = LOW
RESET SHORT
END OF RESET
PULSE (t
)
RP2
)
RP1
POWER OFF
END OF (t
)
POFF
PULSE