ADP5043

Manufacturer Part NumberADP5043
DescriptionMicro-PMU with 0.8 A Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset
ManufacturerAnalog Devices
ADP5043 datasheet
 


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Data Sheet
FEATURES
Input voltage range: 2.3 V to 5.5 V
One 800 mA buck regulator
One 300 mA LDO
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: ±1%
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open-drain processor reset with threshold monitoring
±1.5% threshold accuracy over the full temperate range
Guaranteed reset output valid to V
= 1 V
CC
Dual watchdog for secure systems
Watchdog 1 controls reset
Watchdog 2 controls reset and regulators power cycle
Buck regulator key specifications
Current-mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100% duty cycle low dropout mode
LDO key specifications
Low V
from 1.7 V to 5.5 V
IN
Stable with1 µF ceramic output capacitors
High PSRR, 60 dB up to 1 kHz/10 kHz
Low output noise
Low dropout voltage: 150 mV at 300 mA load
−40°C to +125°C junction temperature range
VIN1 = 2.3V
TO 5.5V
4.7µF
VIN2 = 1.7V
TO 5.5V
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Micro PMU with 800 mA Buck, 300 mA LDO,
Supervisory, Watchdog, and Manual Rese
GENERAL DESCRIPTION
The ADP5043 combines one high performance buck regulator
and one low dropout regulator (LDO) in a small 20-lead LFCSP
to meet demanding performance and board space requirements.
The high switching frequency of the buck regulator enables use
of tiny multilayer external components and minimizes board space.
The MODE pin selects the buck’s mode of operation. When set
to logic high, the buck regulator operates in forced PWM mode.
When the MODE pin is set to logic low, the buck regulator
operates in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold,
the regulator operates in power save mode (PSM) improving
the light-load efficiency.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5043 LDO extend the battery life of
portable devices. The LDO maintains a power supply rejection
of greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.
Each regulator is activated by a high level on the respective
enable pin. The ADP5043 is available with factory programmable
default output voltages and can be set to a wide range of options.
The ADP5043 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. The ADP5043 also provides
power-on reset signals. An on-chip dual watchdog timer can
reset the microprocessor or power cycle the system (Watchdog 2)
if it fails to strobe within a preset timeout period.
HIGH LEVEL BLOCK DIAGRAM
ADP5043
AVIN
R
FILT
AVIN
30Ω
VIN1
BUCK
C5
EN_BK
ON
MODE
EN1
OFF
VOUT2
VIN2
LDO
C1
EN_LDO
1µF
ON
EN2
OFF
AVIN
nRSTO
MR
NC
NC
GND
AGND
GND
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
ADP5043
L1
1µH
SW
V
@
OUT1
800mA
VOUT1
C6
10µF
PGND
FPWM
PSM/PWM
V
@
OUT2
300mA
C2
1µF
WSTAT
WDI1
WDI2
VIN
WMOD
WD1 MODE
SELECTION
©2011 Analog Devices, Inc. All rights reserved.
t
www.analog.com

ADP5043 Summary of contents

  • Page 1

    ... The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5043 LDO extend the battery life of portable devices. The LDO maintains a power supply rejection of greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage ...

  • Page 2

    ... ADP5043 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 High Level Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 General Specifications ................................................................. 3 Supervisory Specifications .......................................................... 3 Buck Specifications ....................................................................... 5 LDO Specifications ...................................................................... 5 Input and Output Capacitor, Recommended Specifications .. 6 Absolute Maximum Ratings ............................................................ 7 Thermal Data ................................................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ...

  • Page 3

    ... AVIN = 3.6 V, EN1 = EN2 = VIN1 25°C, sensed on VOUTx −40°C to +125°C, sensed µ − OUT µs VIN1 falling at 1 mV/µ sec ADP5043 Typ Max Unit 2. 0.1 µA 2 µA 150 °C 20 °C V 0.4 V 0.05 µA 1 µ ...

  • Page 4

    ... ADP5043 Parameter Watchdog 2 Timeout Period (t ) WD2 Option A Option B Option C Option D Option E Option F Option G Option H Watchdog 2 Power Off Period (t ) POFF Option A Option B WDI1 Pulse Width WDI2 Pulse Width Watchdog Status Timeout Period (t WDCLEAR WDI1 Input Current (Source) WDI1 Input Current (Sink) WDI2 Internal Pull-Down ...

  • Page 5

    ... OUT2 OUT 100 µA < I < 300 mA OUT VIN2 = (VOUT2 + 0 5.5 V 100 µA < I < 300 mA OUT VIN2 = (VOUT2 + 0 5 −40°C to +125°C J Rev Page ADP5043 = 10 µF, and T = 25°C OUT A Min Typ Max Unit 2.3 5.5 V − − −3 ...

  • Page 6

    ... ADP5043 Parameter REGULATION Line Regulation Load Regulation 1 DROPOUT VOLTAGE 2 ACTIVE PULL-DOWN START-UP TIME CURRENT-LIMIT THRESHOLD 3 OUTPUT NOISE POWER SUPPLY REJECTION RATIO 1 Based on an end-point calculation using 1 mA and 100 mA loads. 2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2 ...

  • Page 7

    ... THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP5043 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temper- ature may have to be derated ...

  • Page 8

    ... Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled Manual Reset Input, Active Low. TP AGND Analog Ground (TP = Exposed Thermal Pad). Exposed pad should be connected to AGND WSTAT VOUT2 ADP5043 VIN2 3 13 GND TOP VIEW EN2 4 12 WDI2 (Not to Scale) nRSTO 5 11 VOUT1 NOTES 1 ...

  • Page 9

    ... OUTPUT CURRENT (A) 1.795 1.794 +85°C 1.793 1.792 +25°C 1.791 1.790 1.789 1.788 1.787 1.786 –40°C 1.785 1.784 0 0.1 0.2 0.3 0.4 0.5 OUTPUT CURRENT (A) PWM Mode ADP5043 –40°C +25°C +85°C 0.8 0.9 1.0 = 3.3 V, Auto Mode OUT1 –40°C +25°C +85°C 0.6 0.7 0.8 = 1.8 V, Auto Mode OUT1 0.6 0.7 0.8 = 1.8 V, OUT1 ...

  • Page 10

    ... ADP5043 1.797 1.796 1.795 V = 5.5V IN 1.794 V = 4.5V IN 1.793 V = 3.6V IN 1.792 1.791 1.790 0 0.1 0.2 0.3 0.4 0.5 OUTPUT CURRENT (A) Figure 9. Buck Load Regulation Across Input Voltage, V PWM Mode 100 0.0001 0.001 0.01 OUTPUT CURRENT (A) Figure 10. Buck Efficiency vs. Load Current, Across Input Voltage ...

  • Page 11

    ... Figure 18. Buck Switching Frequency vs. Output Current, Across OUT1 CH1 0.1 1 CH2 CH3 Figure 19. Typical Waveforms 1.8 V, OUT1 CH1 CH2 5.6 CH3 Figure 20. Typical Waveforms 1.8 V OUT1 Rev Page ADP5043 –40°C +25°C +85°C 0.1 0.2 0.3 0.4 0.5 0.6 0.7 OUTPUT CURRENT (A) Temperature 1.8 V, PWM Mode OUT1 VOUT 20.0mV/DIV 20.0M A CH1 2.4mV 5.0µ ...

  • Page 12

    ... ADP5043 VOUTx 2.0V/DIV 1MΩ B CH1 20.0M A CH1 W B CH2 50.0mV/DIV 20. CH3 500mA/DIV 20.0M W Figure 21. Typical Waveforms 1 OUT1 VOUTx CH1 20.0mV/DIV 20.0M A CH1 W 200mA/DIV 1MΩ B CH2 20.0M W 2.0V/DIV 1MΩ B CH3 20.0M W Figure 22. Typical Waveforms 3 OUT1 VINx VOUTx 2 SW ...

  • Page 13

    ... OUTPUT CURRENT (A) Figure 31. LDO Load Regulation Across Temperature 3.3 V OUT2 3.325 100µA 1mA 3.320 10mA 100mA 150mA 3.315 3.310 3.305 3.300 3.295 3.290 3.285 3.280 3.5 4.5 5.0 INPUT VOLTAGE (V) Figure 32. LDO Line Regulation Across Output Load, V ADP5043 0.1 = 3.3 V OUT2 0.1 = 3.6 V, IN2 5.5 = 3.3 V OUT2 ...

  • Page 14

    ... ADP5043 250 200 150 100 0.05 0.10 LOAD (A) Figure 33. LDO Ground Current vs. Output Load, V 0.50 1µA 100µA 0.45 1mA 10mA 0.40 100mA 150mA 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 2.3 2.8 3.3 3.8 4.3 INPUT VOLTAGE (V) Figure 34. LDO Ground Current vs. Input Voltage, Across Output Load 2.8 V OUT2 IOUT 3 VOUT CH3 CH1 50mV/DIV 1MΩ ...

  • Page 15

    ... FREQUENCY (Hz) Figure 41. LDO PSRR vs. Frequency 3 IN2 –10 1mA 10mA –20 100mA 200mA –30 –40 –50 –60 –70 –80 –90 –100 10 100 1k 10k 100k FREQUENCY (Hz) Figure 42. LDO PSRR vs. Frequency IN2 ADP5043 1M 10M = 2.8 V OUT2 1M 10M = 3.3 V OUT2 ...

  • Page 16

    ... SEL OPMODE_FUSES ADP5043 POWER MANAGEMENT UNIT The ADP5043 is a micro power management unit (micro PMU) combing one step-down (buck) dc-to-dc regulator, one low dropout linear regulator (LDO), and a supervisory circuit, with dual watchdog, for processor control. The regulators are activated by a logic level high applied to the respective EN pins. EN1 controls the buck regulator while EN2 controls the LDO ...

  • Page 17

    ... Undervoltage Lockout To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the ADP5043. If the input voltage on AVIN drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channel, both the power switch and the synchronous rectifier turn off. When the voltage on AVIN rises above the UVLO threshold, the part is enabled once more ...

  • Page 18

    ... Manual Reset Input The ADP5043 features a manual reset input ( MR ) which, when driven low, asserts the reset output. When MR transitions from low-to-high, reset remains asserted for the duration of the reset active timeout period before deasserting. The MR input has a 52 kΩ ...

  • Page 19

    ... Data Sheet Watchdog 1 Input The ADP5043 features a watchdog timer that monitors microprocessor activity. The watchdog timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (WDI1), which detects pulses as short as 80 ns. If the timer counts through the preset watchdog timeout period ( output reset is asserted ...

  • Page 20

    ... ADP5043 Watchdog Status Indicator In addition to the dual watchdog function, the ADP5043 features a watchdog status monitor available on the WSTAT pin. This pin can be queried by the external processor to determine the origin of a reset. WSTAT is an open-drain output. WSTAT outputs a logic level depending on the condition that has generated a reset ...

  • Page 21

    ... Figure 48. Typical Applications Circuit Inductor The high switching frequency of the buck regulator of the ADP5043 allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 μH and 3 μH. Suggested inductors are shown in Table 11. The peak-to-peak inductor current ripple is calculated using the following equation: × ...

  • Page 22

    ... LDO CAPACITOR SELECTION Output Capacitor The ADP5043 LDO is designed for operation with small, space- saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω ...

  • Page 23

    ... Negative-Going V To avoid unnecessary resets caused by fast power supply transients, the ADP5043 is equipped with glitch rejection circuitry. The typical performance characteristic in Figure 52 plots the monitored rail voltage, V curve shows combinations of transient magnitude and duration for which a reset is not generated for a 2 ...

  • Page 24

    ... Watchdog 1 is kept refreshed or environmental conditions that may unset or damage the processor port controlling the WDI1 pin. In the event of a Watchdog 2 timeout, the ADP5043 power cycles all the supplied rails to guarantee a clean processor start. PCB LAYOUT GUIDELINES ...

  • Page 25

    ... Data Sheet POWER DISSIPATION/THERMAL CONSIDERATIONS The ADP5043 is a highly efficient micro PMU, and in most cases the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and with maximum loading conditions, the junction temperature can reach the maximum allowable operating limit (125° ...

  • Page 26

    ... RISE FALL switching node, SW. For the ADP5043, the rise and fall times of SW are in the order of 5 ns. If the equations and parameters previously given are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers ...

  • Page 27

    ... PGND TP12 MODE TP2 V @ OUT2 300mA C2 1µF TP11 TP9 TP10 WDI1 TP7 WDI2 TP3 6 6 1uF 10 V/XR 5 0402 MR MR WDI 1 WDI 1 WMOD MOD MODE MODE G GND VIAs LEGEND: PPL = POWER PLANE (+4V) GPL = GROUND PLANE TOP LAYER 2ND LAYER ADP5043 ...

  • Page 28

    ... FILT L1 1 µH, 0.09 Ω, 290 mA 1 µH, 0.08 Ω, 230 mA IC1 Dual regulator micro PMU APPLICATION DIAGRAM VIN1 = 2.3V TO 5.5V VIN2 = 1.7V TO 5.5V PUSH-BUTTON Part Number LMK105BJ105MV-F LMK107BJ475MA-T JMK107BJ106MA-T BRC1608T1R0M GLFR1608T1R0M-LR ADP5043 AVIN R FILT 30Ω AVIN SW 6 BUCK 8 VOUT1 11 VIN1 PGND 7 9 EN_BK C5 4.7µF MODE ...

  • Page 29

    ... Typ Max 200 280 400 560 Monitored Rail VOUT1 pin Reserved VOUT2 pin AVIN 1 pin Rev Page ADP5043 T = −40°C to +85°C A Min Max Unit 4.700 V 3.003 3.157 V 2.857 3.000 V 2.564 2.696 V 2.438 2.563 V 2.385 V 2.099 V 1 ...

  • Page 30

    ... SEATING PLANE ORDERING GUIDE 1, 2 Model Regulator Settings ADP5043ACPZ-1- 1.5 V OUT1 V = 3.3 V OUT2 UVLO = 2.25 V Sequencing: LDO, buck ADP5043CP-1-EVALZ RoHS Compliant Part. 2 Monitoring ambient temperature does not guarantee that the junction temperature (T Considerations section for more information. 4.10 0.30 4.00 SQ 0.25 3.90 0.20 16 0.50 15 BSC EXPOSED ...

  • Page 31

    ... Data Sheet NOTES Rev Page ADP5043 ...

  • Page 32

    ... ADP5043 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09682-0-10/11(A) Rev Page Data Sheet ...