ADP5043 Analog Devices, ADP5043 Datasheet - Page 19

• Manufacturer Part Number: ADP5043
• Description: Micro-PMU with 0.8 A Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset
• Manufacturer: Analog Devices

Data Sheet
Watchdog 1 Input
The ADP5043 features a watchdog timer that monitors
microprocessor activity. The watchdog timer circuit is cleared
with every low-to-high or high-to-low logic transition on the
watchdog input pin (WDI1), which detects pulses as short as
80 ns. If the timer counts through the preset watchdog timeout
period (t
required to toggle the WDI1 pin to avoid being reset. Failure of
the microprocessor to toggle WDI1 within the timeout period,
therefore, indicates a code execution error, and the reset pulse
generated restarts the microprocessor into a known state.
As well as logic transitions on WDI1, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
the monitored rail. When reset is asserted, the watchdog timer
is cleared and does not begin counting again until reset deasserts.
Watchdog 1 timer can be disabled by leaving WDI1 floating or
by three-stating the WDI1 driver. The pin WMOD controls the
Watchdog 1 operating mode. If WMOD is set to logic level low,
Watchdog 1 is enabled as long as WDI1 is not in three-state. If
WMOD is set to logic level high, Watchdog 1 is always active
and cannot be disabled by a three-state condition. WMOD
input has an internal 200 kΩ pull-down resistor.
Watchdog 1 timeout is factory set to two possible values, as
indicated in Table 18.
V
SENSED
n RSTO
WDI1
1V
0V
0V
0V
WD1
), an output reset is asserted. The microprocessor is
Figure 45. Watchdog 1 Timing Diagram
V
t
RP1
TH
AVIN/VINx/ENx
WSTAT
nRSTO
VOUT1
VOUT2
WDI2
0V
0V
0V
0V
Figure 46. Watchdog 2 Timing Diagram (Assuming That VOUT2 Is the Monitored Rail)
t
D1
t
WD1
t
t
D2
V
RP1
TH
t
RP1
Rev. A | Page 19 of 32
t
t
WD2
RP2
Watchdog 2 Input
The ADP5043 features an additional watchdog timer that
monitors microprocessor activity in parallel with the first watchdog
but with a much longer timeout. This provides additional security
and safety in case Watchdog 1 is incorrectly strobed. A timer
circuit is cleared with every low-to-high or high-to-low logic
transition on the watchdog input pin (WDI2), which detects pulses
as short as 8 µs. If the timer counts through the preset watchdog
timeout period (t
cycle of all regulators. The microprocessor is required to toggle
the WDI2 pin to avoid being reset and powered down. Failure
of the microprocessor to toggle WDI2 within the timeout period,
therefore, indicates a code execution error, and the reset output
nRSTO is forced low for
off for the t
reactivated according to a predefined sequence (see Table 9).
Finally, the reset line (nRSTO) is asserted for
tees a clean power-up of the system and proper reset.
As well as logic transitions on WDI2, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condition
on the V
between VOUT1, VOUT2, and AVIN (see Table 21). When
reset is asserted, the watchdog timer is cleared and does not
begin counting again until reset deasserts.
Watchdog 2 timeout is factory set to seven possible values as
indicated in Table 19. One additional option allows Watchdog 2
to be factory disabled.
TH
t
POFF
POFF
monitored rail which can be factory programmable
time. After the t
WD2
), reset is asserted, followed by a power
t
t
D1
RP1
t
D2
t
RP2
t
WDCLEAR
.
Then, all the regulators are turned
POFF
period, the regulators are
t
RP1
. This guaran-
ADP5043