ADP5043 Analog Devices, ADP5043 Datasheet - Page 23

• Manufacturer Part Number: ADP5043
• Description: Micro-PMU with 0.8 A Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset
• Manufacturer: Analog Devices

Data Sheet
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5043 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary tempe-
rature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are highly recommended
for best performance. Y5V and Z5U dielectrics are not
recommended for use with any LDO because of their poor
temperature and dc bias characteristics.
Figure 51 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C tempera-
ture range and is not a function of package or voltage rating.
Use the following equation to determine the worst-case capa-
citance accounting for capacitor variation over temperature,
component tolerance, and voltage.
where:
C
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
BIAS
C
is the effective capacitance at the operating voltage.
EFF
1.2
1.0
0.8
0.6
0.4
0.2
0
0
= C
Figure 51. Capacitance vs. Voltage Characteristic
BIAS
× (1 − TEMPCO) × (1 − TOL)
1
DC BIAS VOLTAGE (V)
2
3
4
5
6
Rev. A | Page 23 of 32
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C
Substituting these values into the following equation yields:
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5043, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
SUPERVISORY SECTION
Watchdog 1 Input Current
To minimize watchdog input current (and minimize overall
power consumption), leave WDI1 low for the majority of the
watchdog timeout period. When driven high, WDI1 can draw
as much as 25 µA. Pulsing WDI1 low-to-high-to-low at a low
duty cycle reduces the effect of the large input current. When
WDI1 is unconnected and WMOD is set to logic level low, a
window comparator disconnects the watchdog timer from the
reset output circuitry so that reset is not asserted when the
watchdog timer times out.
Negative-Going V
To avoid unnecessary resets caused by fast power supply transients,
the ADP5043 is equipped with glitch rejection circuitry. The typical
performance characteristic in Figure 52 plots the monitored rail
voltage, V
curve shows combinations of transient magnitude and duration
for which a reset is not generated for a 2.93 V reset threshold
part. For example, with the 2.93 V threshold, a transient that
goes 100 mV below the threshold and lasts 8 µs typically does
not cause a reset, but if the transient is any larger in magnitude
or duration, a reset is generated.
C
1000
900
800
700
600
500
400
300
200
100
EFF
0
0.1
= 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
TH
Figure 52. Maximum V
, transient duration vs. the transient magnitude. The
BIAS
COMPARATOR OVERDRIVE (% OF V
CC
is 0.94 μF at 1.8 V as shown in Figure 51.
Transients
Threshold Overdrive
1
TH
Transient Duration vs. Reset
10
TH
)
ADP5043
100