IC RCVR DGTL 192KHZ 28QFN COMM

 

CS8416-CNZ

Manufacturer Part NumberCS8416-CNZ
DescriptionIC RCVR DGTL 192KHZ 28QFN COMM
ManufacturerCirrus Logic Inc
TypeDigital Audio Interface Receiver
CS8416-CNZ datasheets

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Warranty: 60 days

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Specifications of CS8416-CNZ

ApplicationsDigital AudioMounting TypeSurface Mount
Package / Case28-QFNAudio Control TypeDigital
Control InterfaceI2C, SPIControl / Process ApplicationAV & DVD Receivers, CD-R, Digital Mixing Consoles
Supply Voltage Range3.13V To 5.25V, 3.13V To 3.46VLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use With598-1017 - BOARD EVAL FOR CS8416 RCVROther names598-1723
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2. PIN DESCRIPTION - SOFTWARE MODE
2.1
TSSOP Pin Description
RXP3
RXP2
RXP1
RXP0
RXN
VA
AGND
FILT
RST
RXP4
RXP5
RXP6
RXP7
AD0 / CS
Pin
Pin #
Name
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise
VA
6
as possible since noise on this pin will directly affect the jitter performance of the recovered clock
VD
23
Digital Power (Input) – Digital core power supply. Nominally +3.3 V
VL
21
Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-
AGND
7
nected to a common ground area under the chip.
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected
DGND
22
to a common ground area under the chip.
Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset.
RST
9
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase.
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.
FILT
8
For minimum PLL jitter, return the ground end of the filter network directly to AGND. See
page 53
for more information on the PLL and the external components.
RXP0
4
RXP1
3
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
RXP2
2
S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select
RXP3
1
line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-
RXP4
10
ing or tied to AGND. See
RXP5
11
ommended input circuits.
RXP6
12
RXP7
13
12
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
Top-Down View
28-pin SOIC/TSSOP
13
16
Package
14
15
Pin Description
“External AES3/SPDIF/IEC60958 Receiver Components” on page 49
CS8416
OLRCK
OSCLK
SDOUT
OMCK
RMCK
VD
DGND
VL
GPO0
GPO1
AD2 / GPO2
SDA / CDOUT
SCL / CCLK
AD1 / CDIN
“PLL Filter” on
for rec-
DS578F3