TDA7505 STMicroelectronics, TDA7505 Datasheet
TDA7505
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TDA7505 Summary of contents
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... Device summary Order code TDA7505 October 2007 Car radio DSP for advanced signal processing ■ 5V-tolerant 3V I/O interface ■ Multifunction general purpose I/O ports Description The TDA7505 is an MPX-sampling DSP for car radio applications. Package LQFP100 Rev 1 TDA7505 LQFP100 (14x14x1.4mm) Packing Tray 1/38 www ...
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... Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . 16 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 17 High voltage CMOS interface DC electrical characteristics . . . . . . . . . . 17 DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data and program memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Serial audio interface (SAI Serial peripheral interface (SPI Sony/Philips digital interface (S/PDIF I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TDA7505 ...
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... TDA7505 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 5.2.12 5.2.13 5.2.14 6 Software features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1 AM/FM base band signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 Generic audio signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 TAPE signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 CD signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5 Audiophile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6 Audio decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.7 Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.8 Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 Revision history ...
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... ADC electrical characteristics - measurement bandwidth 10Hz to 53kHz . . . . . . . . . . . . . 25 Table 24. ADC electrical characteristics - measurement bandwidth 10Hz to 192kHz . . . . . . . . . . . . 25 Table 25. Level ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 26. DAC Performance Table 27. FM stereo decoder (SW Table 28. Examples of convenient clock schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 29. Example of possible modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 30. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4/38 TDA7505 ...
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... TDA7505 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. LQFP100 pins connection (top view Figure 3. SAI interface timing - receiver Figure 4. SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. SAI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 Figure Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Debug port serial clock timing Figure 10 ...
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... Overview 1 Overview The TDA7505 integrates two 75 MIPS DSP cores. One core is used for stereo decoding, noise blanking, weak signal processing, Dolby B, music search and MP3 decoding. The second core is used for audio and sound processing and Echo & Noise cancellation. All functions are realized in SW and thus are flexible on customer request ...
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... TDA7505 2 Block diagram Figure 1. Block diagram CD Navi . analog audio in CC Tel Qdiff . Diff . Input Source Selector ADC - ref ΣΔ ΣΔ ADCVDD Decimation Audio ADCGND AVDD AGND CLK in Crystal 8.55 MHz Oscillator 6 Ch. Audio Bus 2 SAI 6ch. receive bit&word clk ...
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... Display SPI SI (slave mode) Display SPI MO (master mode) GPIO input GPIO output Display SPI SS slave select DSP0 external interrupt (IRQA) GPIO input GPIO output External clock input for PLL Display SPI clock (slave mode) Display SPI clock (master mode) Function TDA7505 ...
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... TDA7505 Table 2. Pin description (continued) Reset N° Name Type State RDSCS - 14 I/O DSP0 GPIO2 DSP0 GPIO2 INT - 15 RDSINT I/O DSP0 GPIO3 DSP0 GPIO3 N° Name Type 16 VDD3V3_1 S 17 GND3V3_1 S SCKM input SCKM output 18 SCL bi-direct I/O DSP0 GPIO4 DSP0 GPIO4 Reset N° ...
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... EMI DRAM Address 4 EMI SRAM Address 5 EMI DRAM Address 5 EMI SRAM Address 6 EMI DRAM Address 6 EMI SRAM Address 7 EMI DRAM Address 7 EMI SRAM Address 8 EMI DRAM Address 8 I/O Function EMI SRAM Address 9 EMI DRAM Address 9 EMI SRAM Address 10 EMI DRAM Address 10 TDA7505 ...
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... TDA7505 Table 2. Pin description (continued) Reset N° Name Type state SRA<11> SRA<11> SRA<12> SRA<12> N° Name Type 45 VDD1V8_2 S GND1V8_2 & GND3V3_3 47 VDD3V3_3 S Reset N° Name Type state 48 DRD O 49 DWR O CAS 50 O SRA<13> 51 SRA<14> O SRA<15> 52 DSP0 GPIO8 I/O DSP0 GPIO8 INOUTA SRA< ...
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... GPIO input GPIO output Function I/O Function Multi function I/O GPIO input GPIO output Multi function I/O Debug clock Chip status 1 GPIO input GPIO output Debug output GPIO input GPIO output I/O Function Debug input Chip status 0 GPIO input GPIO output TDA7505 ...
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... TDA7505 Table 2. Pin description (continued) Reset N° Name Type state 68 Debug/Test_Sel0 Debug/Test_Sel1 INOUTK I/O N° Name Type 71 VDD1V8_3 S 72 GNDSUB_D S N° Name Type 73 LEVEL_AM/FM A Signal input to level ADC (single ended) 74 MPX_AM+ A Signal input tuner AM (quasi differential) 75 MPX_AM/FM- A Signal input tuner common ground (quasi differential) ...
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... DBCK_OS1 65 DSP0/1 GPIO9 64 INOUTJ 63 DSP1 GPIO8 INOUTI 62 GND3V3_4 SAI/SPDIF 61 VDD3V3_4 DSP1 GPIO7 60 INOUTH 59 INOUTG DSP1 GPIO6 58 INOUTF/SRA<21>/RAS DSP1 GPIO5 57 INOUTE/SRA<20> DSP1 GPIO4 56 INOUTD/SRA<19> DSP1 GPIO3 55 INOUTC/SRA<18> DSP1 GPIO2 54 INOUTB/SRA<17> DSP1 GPIO1 53 DSP1 GPIO0 INOUTA/SRA<16> Bootsel2 52 SRA<15> DSP0 GPIO8 51 SRA<14> TDA7505 ...
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... TDA7505 4 Electrical specifications 4.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Power supplies digital VDD1V8 I/O VDD3V3 Analog AVDD DACVDD DAC ADCVDD ADC Analog input or output voltage Digital input or output voltage, 5V tolerant T Operating temperature range op T Storage temperature stg 1. The maximum difference in the voltage of AVDD, DACVDD, ADCVDD, analog inputs and analog outputs must not exceed 0 ...
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... Digital power supply @ 1.8V Digital IO power supply @ 3.3V DAC analog power supply @ 3.3V ADC analog power supply @ 3. °C amb Test condition (1) (1) connected through pin XTI connected through pin CLKIN TDA7505 Min. Typ. Max. 1.7 1.8 1.9 3.15 3.3 3.49 3.15 3 ...
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... TDA7505 4.3.4 General interface electrical characteristics Table 8. General interface electrical characteristics Symbol Parameter Low level input current without pull- device High level input current without pull- device Tri-state output leakage without pull I oz up/down device 5V tolerant tri-state output leakage I ozFT without pull up/down device ...
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... SCKT (TCKP=0) 18/38 Valid Valid t t lrckrs lrckrh t t sdis sdih t t sckrl sckrh t sckr Description dsp Valid Valid t t lrckts lrckth scktl sckth t sckt TDA7505 Min Typ Max Unit 13. DSP T ns DSP T ns DSP T ns DSP T ns DSP 0. sckr 0. sckr ...
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... TDA7505 Table 12. SAI interface timing - transmitter Timing (1) T Internal DSP clock period (typical 1/75MHz) DSP t Minimum clock cycle sckt t LRCKT setup time lrckts t LRCKT hold time lrckth t SCKT active edge to data out valid dt t Minimum SCKT high time sckth t Minimum SCKT low time scktl 1 ...
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... MOSI hold time hold t SCK high time sclkh t SCK high low sclkl t SS setup time sssetup t SS hold time sshold 20/38 V alid V alid t t setup hold dtr sssetup sshold t t sclkl sclkh t sclk Description TDA7505 Min Typ Max Unit 13. DSP 0 sclk 0 sclk DSP ...
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... TDA7505 Figure 7. SPI clocking scheme SS (CPOL=0,CPHA=0) SCK SCK (CPOL=0,CPHA=1) SCK (CPOL=1,CPHA=0) (CPOL=1,CPHA=1) SCK MISO MOSI 2 4 Timing 2 Figure Timing 2 Table 15 Timing Symbol Parameter F SCLl clock frequency SCL Bus free between a STOP and t BUF Start Condition Hold time (repeated) START t condition. After this period, the first ...
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... C bus condition Min – 4 250 – Test condition EDTM=0, 16 bit word EDTM=0, 24 bit word EDTM=1, 16 bit word EDTM=1, 24 bit word Test condition Test condition TDA7505 2 Fast mode I C bus Unit Max. Min. Max. 300 20+0.1Cb 300 – 0.6 – – 100 – ...
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... TDA7505 Table 19. Debug port interface (continued) No. Characteristics (Fdsp = 75MHz) 8 DBCK high to DBOUT invalid 9 DBIN valid to DBCK low (set-up) 10 DBCK low to DBIN invalid (hold) DBOUT (ACK) asserted to first DBCK high DBOUT (ACK) assertion width Last DBCK low of read register to first DBCK 11 high of next command ...
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... No input signal decimation Input signal decimation by 2 0–0.4110 Fsin @ f s Test condition TDA7505 (Last) (Note 1) (8) (12) D02AU1369 (NEXT COMMAND) D02AU1370 min typ max ...
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... TDA7505 Table 22. ADC electrical characteristics - measurement bandwidth 10Hz to 20kHz (T = 25°C, ADCVDD = 3.3V, A-weighted filter.) amb Symbol Parameter V Input voltage dynamic range in f Sampling rate s (1) DR Dynamic range SNR Signal to noise ratio THD+N Total harmonic distortion + noise 1kHz; -3dB analog input ...
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... Test condition 1kHz; -1dBFS, flat 1kHz;IEC61606 A-weighted RMS 1kHz; -60dBFS; IEC61606 A-weighted RMS IEC61606 A-weighted RMS 1kHz; 0dBFS 1kHz; 0dBFS 1kHz; 0dBFS Test condition -3dB analog input 1kHz; -3dB analog input; mono TDA7505 Min. Typ. Max. Unit -90 dB -90 dB 100 dB 100 ...
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... Functional description The TDA7505 is broken up into three distinct blocks. One block contains the two DSP Cores and their associated peripherals. The second contains the analog modules ADC with input multiplexer and level adjust and the DAC. The third module contains the RDS processing: filter, demodulator, decoder with error correction and the I and interrupts output ...
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... This is a 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from the Data ALU of the DSP core. 28/38 Section 5.2.12: CODEC on page TDA7505 32) ...
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... TDA7505 Program RAM This is a 24-Bit Single Port SRAM used for storing and executing program code. The 16-Bit PRAM Address, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching, and by the AGU in the case of the Move Program Memory (MOVEM) Instruction ...
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... Refresh rate for DRAM can be chosen among eight divider factors ● SRAM relative addressing mode; 2 ● Four SRAM Timing choices ● Two Read Offset Registers 30/ specification including the highs peed (400 2 C bus has its own unique address whether CPU 256M bit addressable DRAM 22 = 32M bit addressable SRAM TDA7505 ...
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... TDA7505 5.2.7 Debug interface A multiplexed Debug Port is available for the DSP Cores. The debug logic is contained in the core design of the DSP. The features of the Debug Port are listed below: ● Breakpoint Logic ● Trace Logic ● Single stepping ● Instruction Injection ● ...
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... Due to its own interface, it may be considered as an independent function. Thus the module has a separate RDS I SPI. Only the pins are shared with the DSP interfaces. 32/ device address as well as a separate chip select line for the RDS TDA7505 2 C/SPI ...
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... TDA7505 5.2.14 Clock scheme Due to the programmable PLL oscillator, the clock scheme is very flexible. The customer may choose the clock frequency according to the application needs. However one should take into account several constraints: ● The RDS module needs a crystal frequency of 8.55 MHz or alternative an external 74 ...
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... Software features 6 Software features A great flexibility is guaranteed by the two programmable DSP cores. A list of the main software functions, which can be implemented in the TDA7505, is enclosed hereafter: 6.1 AM/FM base band signal processing ● FM weak signal processing ● Integrated 19 kHz Pilot tone filter ● ...
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... TDA7505 6.7 Other ● Voice compression/decompression for traffic information storage ● Echo and noise canceling for mobile phone connection 6.8 Functional modes The SW defines the whole functionality of the device, except RDS. Although ST is able to provide a complete set of SW, the customer may implement his own SW or may use third party SW ...
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... OUTLINE AND MECHANICAL DATA LQFP100 (14x14x1.40mm) Low profile Quad Flat Package 0086901 D TDA7505 ® ...
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... TDA7505 8 Revision history Table 30. Document revision history Date 23-Oct-2007 Revision 1 Initial release. Revision history Changes 37/38 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 38/38 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com TDA7505 ...